Hi team,
customer concerns instability of TMDSCLK of DP source. Please support related questions.
(1) When the TMDSCLK frequency of the source device is not stable, is it possible to control delaying the output to the sink device until it stabilizes?
Is it possible by OE control, register control, etc.?
(2) Are bit3 control and OE control of address 0x09 the same control? If not, please explain the difference.
(3) What happens to the TMDS output when the TMDSCLK frequency in (1) is not stable (e.g., the frequency is 340 MHz or higher)?
Best regards,
Hayashi
