DS125DF410: Duty cycle of REF CLK consult

Stanley Dai

Part Number: DS125DF410

Hi Team,

Customer currently found the duty cycle of their REF CLK is around 44.5%. And our D/S doesn't give such requirements for duty cycle of REF CLK. Do you think are there any risk for customer application here?

Best,

Stanley

over 4 years ago

+1 Clemens Ladisch over 4 years ago

Guru 327630 points

In a daisy chain, after the recommended limit five stages, the typical duty cycle distortion would add up to 2.75 ns. So your 5.5 % appears to be safe.

+1 Drew Miller1 over 4 years ago

TI__Mastermind 43898 points

Hi Stanley,

I agree with Clemens that this probably would not be an issue. The following section of the datasheet has some layout recommendations when it comes to cascading REF_CLK between devices.

Thanks,
Drew

0 Stanley Dai over 4 years ago in reply to Drew Miller1

TI__Expert 5810 points

Hi Drew,

Do we have slew rate requirement for 25M REF CLK, like rise/fall time? I cannot find those info in our D/S.

Best,

Stanley

0 Clemens Ladisch over 4 years ago in reply to Stanley Dai

Guru 327630 points

Even the most demanding logic inputs have a limit of about 25 ns for the rise/fall time. At 25 MHz (pulse length 20 ns), it is not possible for the slew rate to be too slow.

But the REFCLK_IN signal must be digital, not a sine wave.

+1 Drew Miller1 over 4 years ago in reply to Stanley Dai

TI__Mastermind 43898 points

Hi Stanley,

I don't have a specific slew rate requirement for the 25 MHz REF CLK. I think what Clemens mentioned is largely valid, I would suspect a reasonable square wave to be sufficient. I think you could also infer some worst case slew rate from the minimum pulse time and logic low/high levels.

Thanks,
Drew

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DS125DF410: Duty cycle of REF CLK consult