DP83867IS: without active link

Hi May,

Yes it is possible to configure CLK_OUT to 125MHz without active link. However, just want to confirm you are not planning to use this as RX_CLK signal on the MAC, REF input is something different?

Thanks,

David

Hi David,

Just received update from customer, please see details below.

We are planning to use the CLK_OUT 125MHZ as REF CLK for the MAC. Could you explain the root cause of your recommendation. I would have the same concerns if we think about multiple PLL in series. PHY REFCLK 25MHz -> 125MHz PHY PLL CLK_OUT -> MAC 125MHz REF_CLK in -> MAC RGMII PLL ???. Is there a PLL involved in the RGMII MAC? I would expect all is clocked by 125 MHz.
PHY and MAC are running in the same 25MHz clock domain

Thank you.

Regards,
May

Hi May,

RX_CLK is part of the MII signaling and needs to have specific timing relationship to the RX_D0 - RX_D3 lines. CLK_OUT should not be used for this purpose. 

However, it sounds like the REF CLK for the MAC is something different, so this should be fine. 

Thanks,

David

Hi David,

Could you advise how to configure CLK_OUT 125MHZ without valid link? Customer guess its 125 MHz TX_CLK from internal 25 MHz to 125 MHZ PLL

Thank you.

Regards,
May

Hi Maynard,

You can configure the CLK_OUT pin in register 0x170. 

The 125MHz CLK_OUT is generated by PLL from 25MHz reference clock, yes.

Thanks,

David