XIO2001: Clocking and Powerdown Sequence Questions

Hello,

1. The datasheet says that the XIO2001 supports a locally generated clock, so it should not be an issue. The  125MHz single-ended asynchronous clock source option is described in section 8.3.2.3.

2. If any of the recommendations are not followed in the datasheet, then there is no guarantee that the device will work as described.  It does imply in the datasheet that it could be damaged.  What is the difficulty in implementing this sequence?  Is the main concern that you cannot turn off the REFCLK at the appropriate time?

Regards,

Nicholaus

Hi,

Did this answer your question?  Please mark as resolved if so.

Regards,

Nicholaus

Is it okay to use a 100MHz for locally generated clock instead of 125MHz ?

Thank you for the response, Is it okay to use a 100MHz for locally generated clock instead of 125MHz ?

Hi Sumanpreet,

An independent reference clock topology is not supported with the 100MHz reference clock.

"The XIO2001 supports two options for the PCI Express reference clock: a 100-MHz common differential reference clock or a 125-MHz asynchronous single-ended reference clock." 

Regards,

Nicholaus

single-end or differential didn't matter?

Hi Sumanpreet,

If using the 125-MHz asynchronous reference clock.  Then it should be single-ended.

"The single-ended reference clock is attached to the REFCLK+ terminal. The REFCLK+ input, at approximately 20 k Ω , is a high-impedance input. Any clock termination design must account for a high- impedance input. The REFCLK– pin is attached to a 0.1- μ F capacitor. The capacitor’s second pin is connected to VSSA." - Section 8.3.2.3 

Regards,

Nicholaus

Hi Sumanpreet,

Please marked as complete if this answered your question.

Thanks,

Nicholaus