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DP83TC812S-Q1: Vsleep and WAKE pin

Part Number: DP83TC812S-Q1

Hi expert,

I have two questions regarding to the VDDIO/Vsleep and WAKE pin. 

  1. For the power up sequence, what the maximum acceptable delay time spec for Vsleep and VDDIO? In customer's real application, the Vsleep must power on first, then they can enable VDDIO power rail. So they need to consider the delay time spec between VDDIO and Vsleep. Is it limited in 10ms? Customer measure the current delay time between VDDIO and Vsleep which is higher than 10ms. But the 812 can power up into normal mode normally. So just would like to check with you. 

            2. During power up and normal operation, how to deal with WAKE pin? For local wake up from sleep mode, we can pull a >40us high level pulse on WAKE pin. So does it mean that WAKE pin can be kept low in other states? 

Thanks!

Ethan Wen

  • Hi Ethan,

    • Unfortunately, We cannot sign you off when the the current delay time between is higher than 10ms. It is require follow the datasheet requirement.
    • Yes your understanding is correct. WAKE Pin will kept low during other state. It will only pull up temporary during wake up state.

    --

    Regards,

    Hillman Lin

  • Hi Hillman,

    Thanks for your support. 

    Customer measure the delay between VSLEEP and VDDA is about 28.8ms. Please check the waveform as below.  Do you think that is OK? 812 and 720 share the same circuit on the customer's board. Both 720 and 812 can work normally. 

    Beside, customer found the issue about INH. There is a high spike when 720s and 812s VSLEEP on. Please check my attached pictures of the names with “INH spike”. Why is there such a spike on INH? Normally, what status INH should be after power-on?

    720s INH spike - 1

    720s INH spike - 2

    812s INH spike - 1

    812s INH spike - 2


    Regards,

    Ethan Wen

  • Hi Ethan,

    • We check internally 28.8ms delay is ok  between VSLEEP and VDDA.
    • Regarding to the second question, I would like to know is 0.315ms or 0.14ms the ramp up time for the supply voltage (V_Sleep)? Could you increase the ramp up time for the supply voltage (V_Sleep) to see rather it remove the INH spike?

    --

    Thank you,

    Hillman Lin

  • Hi Hillman,

    Thanks for your support. 

    Regarding to the second question, I would like to know is 0.315ms or 0.14ms the ramp up time for the supply voltage (V_Sleep)? Could you increase the ramp up time for the supply voltage (V_Sleep) to see rather it remove the INH spike?

    The VSLEEP power up ramp is about 500us, from 0 to 3.3V. Because the 3.3V is the main power rail in customer's system. So if change the ramp up time of 3.3V, it will affect the other 3.3V load. 

    Do you know if there is any other way to remove the spike? Is it feasible to add an resistor between 3.3V and VSLEEP? If yes, which factors we need to consider? 

    Regards, 

    Ethan Wen

  • Hi Wen,

    Are you able to add one capacitor to ground for the V_sleep pin to increase the ramp up time of the V_Sleep? I do think adding an capacitor is a better solution than adding a resistor to 3.3V since V_sleep depend on discrete LDO compared to other power supply in the PHY.

    --

    Regards,

    Hillman Lin

  • Hi Hillman,

    Customer have 1uF capacitor to ground. 

    For 720s,

    For 812s,

    720s INH spike - 2

    Besides, as showed above, the spike width is about 200us, it seems not a transient noise,  it is hard to remove it just by a little RC circuit. 

    Thanks.  

    Ethan Wen

  • Hi Wen,

    Putting a capacitor in the INH pin can also help with decreasing the Spike on the INH pin. Are you able to do that?

    --

    Regards,

    Hillman Lin