Hi Team,
When PDB is set to Lo (IC is RESET), what is the state of the CSI-2 output pin?
Is it Hi-z?
The SoC connected to the deserializer is an input pin, so if the deserializer is Hi-z, the input is indeterminate.
I thought that an external pull-down for fixing the level would be needed to take care of the input pin.
Is the idea correct?
Best regards.
Hi Okano-San,
Thank you for the question. It is correct. Asserting PDB signal low will power down the device and consume minimum power with CSI-2 Tx outputs in tri-state.
An external RC network on the PDB pin may be connected to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. A 33-kΩ pullup and a 10-μF or higher capacitor to GND are recommended to delay the PDB input signal rise.
Regards,
Josh
