TL16C752D: FIFO Ready Register

Hi Bottini,

It should be what is described on page 38 where it compares the current number of data/bytes against the trigger byte level set. 

Are you seeing something else occuring? 

-Bobby

Hi Bobby,

thank you for your time.
We are still studying the schematic.
Do we have to use the RXRDY signals and can't we just use the FIFO RDY registers (bit0) to understand when to send new messages to the uart ?
Correct?

Hi Bottini,

Either method works. looking at the RXRDY/TXRDY pins requires additional GPIs from the processor but would be a little quicker than trying to access registers from the 752D device so both have advantages/disadvantages. 

You could also do a burst write then check the LSR bit 6 to see when the THR is empty or check IIR for THR interrupts. It all really depends on how you want to set up your system/ISR.

-Bobby

Sorry but all methods are different.

Suppose the trigger level (TLR register) for the transmit FIFO is “52”.

1. Using TXRDY signal (page 27 of the attached manual):
   • TXRDY goes high when the FIFO is FULL (64 chars waiting to be transmitted).
   • TXRDY goes low when there are at least 52 free positions in the FIFO.
2. Using LSR[6] (page 33 of the attached manual):
   • Bit 6 goes high when the FIFO is empty (and the shift register is empty too)
   • Bit 6 goes low when 1 to 64 chars are present in the FIFO (not when the FIFO is full).
3. Using FIFO Read[0/1] (page 38 of the attached manual):
   • Bit 0/1 goes low when there are 0-51 free positions in the FIFO (not necessary when the FIFO is FULL).
   • Bit 0/1 goes high when there 52-64 free positions in the FIFO.

So, if I follow literally the attached manual, when I need to transmit data, the only way to check when the FIFO is full is to look at TXRDY signal.

But, at the first page, the manual says:

With the FIFO RDY register, the software gets the

status of TXRDY or RXRDY for all two ports in one

access

This description of the FIFO RDY register is quite different from the one at page 38:

• With the description at page “0”, the bit 0/1 of the FIFO RDY registers are copies of the TXRDY signals, thus they can be used to check if the FIFO is full.
• With the description at page “33”, the bit 0/1 of the FIFO RDY registers simply indicates if there are more or less than 52 free spaces in the FIFO, but not if the FIFO is full (0 free position).

Can you please clarify if the bits in FIFO RDY registers are the copies of the TXRDY signals or not? If not, please revise the manual because it contains wrong information.

For your reference, I also attached the manual of a compatible device (SC16C752B); the description of the FIFO RDY register is:

0 FIFO Rdy[0] transmit FIFO A status. Related to DMA.

1 FIFO Rdy[1] transmit FIFO B status. Related to DMA.

They refers to the DMA description, which describes the TXRDY signals. So, it seems that FIFO RDY holds the status of TXRDY signals.

Thanks Bobby

Hi Bottini,

I've reached out to one of our designer engineers for this device to see if we can verify the FIFORDY register logic.

I'll let you know when I hear back from him.

-Bobby