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LMH0341: LVDS output bit mappings

Simon Doherty
Prodigy 10 points
Part Number: LMH0341


We're developing a new product based on LMH0341 for HD/3G-SDI applications.

Can you give me a full and complete timing diagram for the serial to parallel conversion of the serial SDI input stream to the LVDS parallel output stream? I need to know how the bit-mappings are done. This is not entirely clear in the datasheet. I _think_ the bit-mappings are like the diagram I have attached, but I'm not sure. Please can you confirm?

Also, what would be the default clock frequency for the RXCLK for:

1) HD-SDI operation?

2) 3G-SDI operation?

Many thanks for your help.

Simon.

  • +1
    TI__Guru* 93570 points

    Hi Simon,

    Your understanding is correct. On each rising or falling edge of the received clock there will be 5 new symbol on RX0 through RX4 LVDS differential pairs. These symbols are sequential - for example symbol A-F-.... on RX0 and B,G,.. on RX1 and etc - as you have noted in your diagram.

    Device auto-detects the data rate and automatically provides corresponding receive clock. LVDS bit ordering is as noted above.

    For SDI applications, there is example FPGA IP that handles these low level and scrambling required by SMPTE. I am not sure if you have access to this FPGA IP - please note this is as is. This example code also generates color bar or other patterns to quickly get your application up and running. If you don't have access to this IP, please send me a friend request along with your company email address so you can access this IP.

    Regards,Nasser

  • +1
    Prodigy 10 points

    Thanks for confirming that my timing diagram is correct Nasser.  I just wanted to be 100% sure ...

    And thanks, I already have access to the example code.  Certainly the video decode module (e.g. descrambling, crc, std detect looks useful).  However, the I/O modules, and clock generation are for an older generation of Xilinx FPGAs that are no longer supported by the latest Xilinx Vivado tools.  These will require some modification to replace the DDR regs and DCM_SP components with up-to-date primitives).

    Regards, Simon.