DP83867IR: Clock Waveforms at 1Gbps

Hi Priya,

I have couple comments and questions on the scope snapshot. Here are the following comments and questions I have:

• From the snapshot you send me, Could you get a snapshot of the signal at the end point? For example, if SoC is sending packet, TX_CLK should be measure close to the SoC. I saw some reflection on the RX_CLK this might be cause by the measurement.
• Please refer to the datasheet table 7.10 and 7.11 for the rise and fall time and other timing constraint.
• Your TX clock signal does not look right. It should be swing between 0 to VDDIO. It seems like the rise and fall time is too big. Does it fall within the datasheet requirement?

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Regards,

Hillman Lin

Hi,

The connections that I have is - Ethernet switch --> Termination Resistor (0ohm) --> PHY Chip.

The switch is BGA package and I am not able to access the pin. The waveform I shared earlier is probed at the resistor end closer to the switch. The trace length between switch and resistor is 213mil. 

I also probed directly on the TX_CLK pin on the PHY chip and it is not very different from the earlier waveform (RGMII2_TXC).

You are right that the rise and fall times are not compliant to the spec. The trace length between the resistor and PHY chip is 1990mil, which I dont think is much. The trace capacitance is ~6.5pF. The application note recommends to minimize the trace lengths below 5000mil.

I tried removing the termination resistor (basically disconnected the PHY) and probed the clock at the same resistor pad closer to the switch and the waveform improves significantly.

So its either the trace or the PHY chip itself loading the signal. PHY datasheet specifies input capacitance as 5pF. Are there any configuration settings that control the input slew rate?

Hi Priya,

Our PHY have a fix impedance on the MAC side. Here are the two possible solutions to fix your issue:

• Are you able to control the rise and fall time or the slew rate on the MAC side?
• If not, Improving the capacitance can help with the slew rate

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Regards,

Hillman Lin