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DP83822HF: MII LOOPBACK FAIL

Part Number: DP83822HF

hi, team
we are using DP83822HF PHY device, and meet some problems, so we need your help.
(1) the interface between MAC and PHY is MII default.
(2) we want try some stress test. for one transfer, data is send from MAC to PHY via MII interface, MII loopback is enabled by setting bit[14] in the BMCR of PHY, the data return to the MAC, MAC check the data, if the data is same and has no error, this data transfer is deemed PASS. the MAC continually send and check data.
(3) the test will fail in MII loopback mode, may fail in several hundreds times or several thousands times, it is random.
(4) we measured the timing of tx path from MAC to PHY, the timing is pass, setup time is about 22ns, hold time is about 18ns. 
(5) we found when fail (in MII loopback), the tx data is send to PHY, and no rx data out from PHY . RX_DV is low when fail, RX_ER is always low, no matter success or fail.
(6) after fail, we read the bit[14] in the BMCR, it is still "1".
(7) the same hardware and software, we try PCS loopback (33500 times pass), digital loopback (280000 times), both no fail.
schematic is attached.
why data is not send out from PHY in last data periord ?
could you help to give some suggestions ? thanks a lot.

to TI.rar

  • Hi Eason,

    It is strange that MII loopback and other PCS and Digital loopback is working since MII loopback come before PCS and Digital loopback. Can I ask some question for further debug?

    • Are you configure any other register when you do the MII loopback. Could write 001F to 8000 or reset the PHY before you program the MII loopback.
    • Why did you need MII loopback?

    --
    Regards,

    Hillman Lin

  • hi, Hillman

    (1) after power up, we hardware reset PHY via hardware reset pin 18.

    (2) we just set 0x6100 at 0x0000 register to enable MII loopback, before test, did not write 001F to 8000, because HW and SW reset has same effect accoding to datasheet.

    (3) why MII loopback, we just want to do some MII interface stress test. but when MII loopback, it failed. PCS and digital loopback pass.

    any suggestions ? is our configuration of MII loopback wrong ?

  • Hi Eason,

    • Which software did you use to read and write the register? USB2MDIO GUI?
    • can you read register 0000 multiple times to double check rather it is actual write the register in 6100
    • Try soft reset after you enable the MII loopback. Write 001F to 4000.

    --

    Regards,

    Hillman Lin

  • Hi Hillman

    (1) we do not use GUI, we have a MAC, we use MAC to read PHY registers via MDIO interface.

    (2) yes, it's 6100, even after MII loopback failed. the register still 6100.

    (3) we tried, register 0x0000 set to 0x6100, then register 0x001f to 0x4000, then begin test, still fail.

  • Hi Eason,

    May I ask what MAC interface are you using when you are performing the MII loopback?

    --
    Regards,

    Hillman Lin

  • hi, Hillman

    we use a synopsys MAC IP, and our FPGA designer integrate DMA/MTL/MAC three parts

    the interface between MAC and PHY is MII, 100M

    BR

  • Hi Eason,

    I will test in the lab later this week for the MII issue you are facing. Meanwhile, could you let me know why are you performing MII loopback?

    --

    Regards,

    Hillman Lin

  • Hi Eason,

    We check the MAC loopback today in lab with RMII interface and it works perfectly fine. We don't have the 822 board with MII interface on it so we are not able to perform this test in lab.

    • Could you probe what you signal are you are having when you enable the MII loopback on COL and CRC pins?
    • Could you tell me the what did you read for the register 0x467? I would like to double check on the strapping.

    --

    Regards,

    Hillman Lin