Drew,
Sorry for the long delay in responding to your question. We have been trying a lot of different things trying to get our setup working.
We also had doubts that our clock was meeting the jitter requirement based on the timing reports from our FPGA compile. We went ahead a built a small PCB with a new clock source to drive the TNETE and the FPGA directly. We should definitely be meeting jitter specs now as the new clock board is a high quality oscillator and clock driver with careful attention paid to impedance matching and signal delay.
The improved clock setup did make things more stable with our setup but we could still not get the part to properly sync with our data in loopback mode. After extensive testing I think we may have stumbled onto the solution but we want to confirm. The datasheet says:
