DS90UB960-Q1: DS90UB960WRTDTQ1

Dear Justin Phan

Thanks very much for your reply!

We encounter problems when EMC testing, 1.6GHz exceed the limit about 16db. 

You can see Spectrum Analyzer scan wave as follow: 

I find a document at end of DS90UB960-Q1 datasheet, the link as follow:

www.ti.com/.../slyt719.pdf

As described in the article, disable REFCLK on the deserializer and try using the internal clock.  Spectrum Analyzer scan result is good. Picture as follow:

According to the above test results, Do you have any suggestion for improve the EMC(Radiated emissions ) test?

Thanks very much!

Hope your reply.

Wang Yuxue

+86 18611758270

Hello Wang,

EMC results are very dependent on the system and requires good design practices for the best performance. There is a bit of a limit on the advice that I can give, since there are several factors in the system that affect EMC, outside of what is known to me. The article that you are referencing is used to identify possible sources of emission and can be used as guidance to apply better shielding. But the 960 does need an oscillator for normal operation, so it cannot be removed from the design.

What specific frequencies are the customer seeing the peaks at? And are you using Synchronous MODE?

In order to address EMC issues, customers can try the following:

1. Apply better grounding and shielding around their device.
   1. Use metal shielding
   2. Use good grounding techniques
   3. Use proper differential layout of PCB traces
   4. Tight trace impedance control
2. Use a different oscillator with a different frequency, to see if that peak can be shifted to a level that allows you to pass the EMC test. The 960 supports a REFCLK oscillator between 23MHz - 26MHz. But changing the oscillator frequency will have effects video bandwidth and other parts of the system that use PLLs, so this is not really an ideal solution unless customer is willing to validate that their system works at a new REFCLK frequency.
3. Customer may also try enabling SSC on their oscillator, when operating in Synchronous mode. The 960 can tolerate a REFCLK with an SSC profile of up to +/-0.5% amplitude deviations (center spread) or up to 1% amplitude deviations (down spread) and up to 33-kHz frequency modulation from a clock source.
4. If you are connecting a 953 to the 960, then you can try using the AON clock mode on the 953 to drive the Forward Channel.
   1. When you use Synchronous mode, you are sending a 25MHz signal from the 960 to the connected serializer, which may appear on EMC tests. Proper grounding and shielding techniques can still be implemented to pass EMC results, but if you cannot improve these aspects in your design, then one work around would be to either use the Non-Synchronous mode on the serializer or the AON clock mode in the 953, which provided inherent spreading without needing an external REFCLK with SSC.
5. If your application can tolerate lower CSI-2 video bandwidth, then you can try lowering the Forward Channel line rate from 4G to 2G.

The solution we recommend is to improve grounding and shielding in your system. Other solutions are possible workarounds. 

Best,

Justin Phan

Dear Justin Phan

Thanks very much for your reply!

The paak frequency at 1.6GHz, we use synchronous MODE.

In our system, wo use 935 connect to 960.

Although it is said that the 960 must have an external 25M REFCLK, it can work without this REFCLK, and from the phenomenon, the radiated energy of the two is very different. Can you help explain why?

Also, is there any way to reduce 960's radiant energy, by modifying the chip's configuration or working mode? and  what impact will it have？

Thanks very much!

Hope your reply.

Wang Yuxue

Hello Wang,

I would recommend reviewing the PCB layout of the boards and improving the design, in order to mitigate EMC concerns. You may reference our 960 EVM for a design with our layout guidelines implemented. Would that be a possible avenue to pursue?

The internal 25MHz REFCLK in the 960 has a 10% tolerance. An external oscillator is needed in order to maintain accurate operation of the 960 PLLs that drive the Back Channel frequency and the TX Port outputs. If an external oscillator is not used, then any PLL that uses the REFCLK signal will deviate as well and you will not be able to meet the specific data rates that are defined in the datasheet. If customer does not use external REFCLK, then we cannot guarantee any of the operating conditions specified in the datasheet.

EMC is a system-level issue that can't be fixed by just changing the 960 chip. My previous post has a few methods that customers can try to help pass EMC tests in their system. If you cannot change the hardware, then I recommend trying to enable SSC on their oscillator part or replacing it with an oscillator that supports SSC within the limits defined in the 960 datasheet.

Another method to try is configuring the 960 in Non-Synchronous Mode and the 935 in AON Non-Synchronous Mode. The AON mode provides inherent spreading, similar to SSC. The only down-side is that your 935 will not be able to generate a CLK_OUT signal in this mode, which I am not sure if is critical in your design.

Another method is to lower the Forward Channel rate from 4Gbps to 2Gbps. Keep in mind that if the Forward Channel is 4Gbps and the Back Channel is 50Mbps, then the channel link is operating between 2GHz - 25MHz. If you lower the Forward Channel rate to 2Gbps, then the link will operate at 1GHz - 12.5MHz in Synchronous mode. This allows you to avoid the 1.6GHz peak in your EMC test. But the downside is that lowering the Forward Channel rate will limit the video throughput that can be transferred from the camera.

Video Throughput = HActive x VActive x FPD x Bits-Per-Pixel x Overhead (Assume 25% if unknown)

Best,

Justin Phan

Hi Justin,

We would like to know, will it help if we change EQ settings? The customer can hardly change the hardware so if we can have some very small changes it helps a lot. Thanks.

BR,

Elec Cheng

Hi Elec,

The EQ settings are related to LOCK. Normally, we recommend keeping the default EQ settings. If customer is losing LOCK periodically, they may adjust the EQ settings based on the MAP results, but we recommend improving the PCB design and cable design instead, in order to make the default EQ settings usable.

But this is a bit off topic. The EQ settings would not affect the EMC testing. Only changing the Forward Channel rate of the connected SER/DES devices or implementing some type of SSC, as I mentioned earlier, would help resolve the issue.

Best,

Justin Phan

Dear Justin

Thanks very much for your reply!

We will try the two type crystal with SS function.

Thanks very much!

Wang Yuxue

Hello Wang,

Keep in mind that the 960 is only capable of tolerating a REFCLK with an SSC profile, as described in the below table:

The "D" option in the table seems to go outside of what the 960 device can tolerate. If there is any results, let me know.

Best,

Justin Phan