DS90UB953-Q1: Delay between Lock and CLKOUT output

Hi David,

Thanks for your question. Do you know if the customer is using register 0x06 and 0x07 to set a specific CLK_OUT frequency? If they are, I believe the majority of the delay in the correct CLK_OUT frequency being transmitted will be due to this I2C transaction.

I can test this out in the lab as well to see if I can get a ballpark idea of what kind of delay we'd be dealing with. I'll be OoO Thursday and Friday, but should be able to get into the lab to check on this early next week. 

Best,

Thomas

Hi Thomas,

The plan is to keep 0x06 and 0x07 as their default values.

Thanks!

David

Hi David,

Thanks for the information. I was able to go into the lab today and found that the clk_out output starts before the forward channel lock is high. This makes sense as the back channel is from the 954 is used as the reference source for the 953 clock, and the clk_out will start to output after the back channel CDR is locked (before the forward channel locks). 

Let me know if you have any questions on this!

Best,

Thomas

Thanks Thomas! By any chance can you grab a scope shot showing the timing of PDB, Lock, and CLK_OUT for a clearer view?

Hi David,

Sure, Let me grab this scope shot this afternoon and get back to you. I'll capture PDB (953), lock (954) and clk_out (953).

Best,

Thomas

This is perfect, thanks so much Thomas!

Your welcome! I'm going to close out this thread but feel free to re-open if you have any additional questions.