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DS160PR421: Cant set SEL_OV and SEL_VAL in linear redriver w/ mux

Part Number: DS160PR421
Other Parts Discussed in Thread: DS160PR412,

We are able to R/W the SHARE and CHANNEL registers of the device over I2C w/ the exception of the SEL_OV at offset 0x0E and SEL_VAL at offset 0x0F.  Are there any pin strappings or other control which prevent setting these bits? 

Also, does setting the mr_rx_det_man at offset 0x3 have the some effect as the L0 pin strapping for RX_DET/SCL which causes "PCI Express RX detection state machine is disabled."

Thanks

  • Hi David,

    If you are able to read share and channel registers, Please let me know which document refers to these two registers(Reg 0x0E and Reg 0x0F).

    Yes rx detect settings can be controlled through the pin or register. For register setting we need to set the override pin.

    Regards,Nasser

  • 1) this is the document and associated register descriptions

     

    SNLU278 – MARCH 2021
    DS160PR412, DS160PR421 Programming Guide

     

     

    2)  double checking – in I2C mode does setting mr_rx_det_man = 1 disable the PCIe RX detection state machine

     

    Thanks,

    Dave

  • Hi Dave,

    1). Thanks for this document reference. I believe you are doing read/modify write operation and you should be able to set the override value(Reg 0x0E[4] and select the input by setting reg 0x0F[[2].Please confirm.

    2). Reg 0x03 bit set forces 50-ohm termination - similar to the RX_DET pin setting at L0. Then to enable regular pcie RX detect we need to set reg 0x03[2] to 1'b0 and reg 0x03[[1]=1'b1 - same as L3 pin setting. 

    Regards,Nasser

  • Hi Nasser,

     

      I can read and write the channel registers as expected and I can read the share register device_id registers.

    However if I try to set bit 2 of share registers 0x0E or 0x0F = 1 they always read back as 0.

     

    Regards,

    Dave

  • Hi Dave,

    I just checked one of the DS160PR421-412 EVM boards and see the same thing as you are reporting. I am able to write into share.reg 0x0F[2] with override enabled already(reg share.0x0E[7:0]=0x3F). However, when i read back i see reg share.0x0F[2] cleared. I am checking on this and will update you within the next 2-3 days.

    Regards,,Nasser

  • Hi Dave,

    After replicating your findings, we've been in lab trying to find a register workaround to enable port selection through register map. However, we haven't been able to find a workaround to do port selection through register settings as noted in the programming guide. We are planning to update the programming guide to reflect this. Meanwhile our only option is to select a port through SEL pin. Please use CPLD or a GPIO to select either port A or port B.

    Regards,Nasser 

  • Hi Nasser,

      Have you verified that all of the registers work as expected? It's hard for us to verify that all  register settings like equalization/gain are working as expected.

    Thanks,

    Dave

  • Hi Dave,

    Yes i have verified in lab that other register settings such as gain are working as expected. 

    Regards,Nasser