Other Parts Discussed in Thread: DS160PR412,
We are able to R/W the SHARE and CHANNEL registers of the device over I2C w/ the exception of the SEL_OV at offset 0x0E and SEL_VAL at offset 0x0F. Are there any pin strappings or other control which prevent setting these bits?
Also, does setting the mr_rx_det_man at offset 0x3 have the some effect as the L0 pin strapping for RX_DET/SCL which causes "PCI Express RX detection state machine is disabled."
Thanks