Other Parts Discussed in Thread: DS90UB914A-CXEVM
Hi,
I'm having a design with DS90UB914 and DS90UB913 and it's working on the lab.
VDD_n=VDDIO=1.8V.
When we measure the power sequence, the rise time of VDDIO (and VDD_n) is 55 to 65 uS, while in the datasheet Table 8 its written that is should be min 50uS max 5mS
We are using the same LDO family as in DS90UB914A-CXEVM Deserializer Board Schematic. In out case P/N: LP38693SD-1.8. But since this device is fast start up (~40uS based on his datasheet), we try to change the Cin and Cout to 22uF in order to have slower rise time, and without any improvement (moved to 60-70uS).
My questions are:
1. If the rise time of DS90UB913/4 will be some times 45 uS, will it affect the device startup?
2. Is so, what are the max value of capacitor we can use for VDDn/VDDIO pins?
3. Another issue is the V(VDD_n) to PDB VIH delay. for the x914 there are no requirement (Table 8) but for the x913 it's t3*=16 mS max (table 8-1).
It's a mistake and also the x914 needs max of 16 mS?
