DS90UB913A-Q1: Suggested Power-Up Sequencing

Hello Kenji,

Kenji Ohno1 said:

If PDB is asserted after the t3 provision, will the bit error be automatically cleared to the default?

The errors are caused by writing to register 0x27 because this resets the forward channel. You will not be able to write to any registers if you have not yet asserted PDB. To clear the bit errors you will need to reset the error counter resisters on the deserializer.

Kenji Ohno1 said:

When the t3 provision cannot be observed, only the 0x27 register is not initialized and needs to be written manually?

When t3 cannot be met, the writes to register 0x27 are used to reset the forward channel. All registers on the 913a should automatically be properly initialized.

Kenji Ohno1 said:

If the 0x27 register cannot be cleared, does the data output start to DES with the error still in the register?

If register 0x27 is not cleared, the forward channel will not be able to function as this register is used to power down the forward channel PLL and NCLK.

Kenji Ohno1 said:

In the case of no register write, I would like to know the problem with t3 > 16ms.

if t3 > 16ms the 0x27 register write is a requirement for correct operation of the device otherwise start-up issues may be experienced.

Best regards,

Joshua 

Hello Kenji,

We cannot guarantee that the problem will be fixed with a power cycle, although it may fix the issue until the next power cycle.

We recommend the register writes to 0x27 to ensure that the startup issues never occur if t3 > 16ms.

You can try to not use the register writes if you have not experienced problems yet, but if you do begin to experience issues on startup please use the register writes.

Best regards,

Joshua

Hi Kenji,

0x27 is the workaround should the required timing sequence not be fulfilled. 

It was identified that only a small sub-set of units have issue under these certain power-up conditions.

Regards, 

Logan