Hello TI experts,
we are currenty struggeling to get the DP83826I PHYs running with Sitara AM243x.
To analyze the problem step-by-step we tried to get the "enet_layer2_icssg"-example from the AM243x SDK (V08.03.00.18) running on our own hardware target, where we use the DP83826I PHYs.
We modified the example.syscfg to match our hardware design:
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@08.03.00"
* @versions {"tool":"1.12.1+2446"}
*/
/**
* Import the modules used in this configuration.
*/
const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1 = gpio.addInstance();
const gpio2 = gpio.addInstance();
const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const i2c2 = i2c.addInstance();
const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1 = pruicss.addInstance();
const pruicss2 = pruicss.addInstance();
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const mpu_armv77 = mpu_armv7.addInstance();
const enet_icss = scripting.addModule("/networking/enet_icss/enet_icss", {}, false);
const enet_icss1 = enet_icss.addInstance();
/**
* Write custom configuration values to the imported modules.
*/
gpio1.$name = "CONFIG_GPIO_RESET1";
gpio1.pinDir = "OUTPUT";
gpio1.GPIO.gpioPin.$assign = "ball.U13";
gpio2.$name = "CONFIG_GPIO_RESET2";
gpio2.pinDir = "OUTPUT";
gpio2.GPIO.gpioPin.$assign = "ball.V7";
i2c1.$name = "CONFIG_I2C0";
i2c1.I2C.$assign = "I2C0";
i2c1.I2C.SCL.$assign = "ball.A18";
i2c1.I2C.SDA.$assign = "ball.B18";
i2c2.$name = "CONFIG_I2C1";
i2c2.I2C.$assign = "I2C1";
i2c2.I2C.SCL.$assign = "ball.C18";
i2c2.I2C.SDA.$assign = "ball.B19";
pruicss2.$name = "CONFIG_PRU_ICSS0";
pruicss2.coreClk = 333333333;
pruicss2.iepClk = 500000000;
udma1.$name = "CONFIG_UDMA_PKTDMA_0";
udma1.instance = "PKTDMA_0";
debug_log.enableUartLog = true;
debug_log.enableCssLog = false;
debug_log.uartLog.$name = "CONFIG_UART0";
mpu_armv71.$name = "CONFIG_MPU_REGION0";
mpu_armv71.size = 31;
mpu_armv71.attributes = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute = false;
mpu_armv72.$name = "CONFIG_MPU_REGION1";
mpu_armv72.size = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv73.$name = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr = 0x41010000;
mpu_armv73.size = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.$name = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr = 0x70000000;
mpu_armv74.size = 23;
mpu_armv75.$name = "CONFIG_MPU_REGION4";
mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv75.baseAddr = 0x80000000;
mpu_armv75.size = 31;
mpu_armv76.$name = "CONFIG_MPU_REGION5";
mpu_armv76.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv76.baseAddr = 0xA5000000;
mpu_armv76.size = 23;
mpu_armv76.attributes = "NonCached";
mpu_armv77.$name = "CONFIG_MPU_REGION6";
mpu_armv77.size = 27;
mpu_armv77.baseAddr = 0x60000000;
enet_icss1.$name = "CONFIG_ENET_ICSS0";
enet_icss1.GigabitSupportEnable = false;
enet_icss1.phyAddr2 = 7;
enet_icss1.phyAddr1 = 3;
enet_icss1.icss = pruicss1;
pruicss1.$name = "CONFIG_PRU_ICSS1";
pruicss1.intcMapping.create(1);
pruicss1.intcMapping[0].$name = "CONFIG_ICSS1_INTC_MAPPING0";
pruicss1.intcMapping[0].event = "41";
pruicss1.intcMapping[0].channel = "7";
pruicss1.intcMapping[0].host = "8";
/**
* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
* re-solve from scratch.
*/
gpio1.GPIO.$suggestSolution = "GPIO0";
gpio2.GPIO.$suggestSolution = "GPIO0";
debug_log.uartLog.UART.$suggestSolution = "USART0";
debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15";
debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16";
enet_icss1.PRU_ICSSG1_MDIO.$suggestSolution = "PRU_ICSSG1_MDIO0";
enet_icss1.PRU_ICSSG1_MDIO.MDC.$suggestSolution = "ball.Y6";
enet_icss1.PRU_ICSSG1_MDIO.MDIO.$suggestSolution = "ball.AA6";
enet_icss1.PRU_ICSSG1_IEP.$suggestSolution = "PRU_ICSSG1_IEP1";
enet_icss1.PRU_ICSSG1_IEP.EDC_LATCH_IN0.$suggestSolution = "ball.Y13";
enet_icss1.PRU_ICSSG1_IEP.EDC_SYNC_OUT0.$suggestSolution = "ball.V12";
enet_icss1.PRU_ICSSG1_MII_G_RT.$suggestSolution = "PRU_ICSSG1_MII_G_RT";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_COL.$suggestSolution = "ball.U15";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_CRS.$suggestSolution = "ball.U14";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD0.$suggestSolution = "ball.Y7";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD1.$suggestSolution = "ball.U8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD2.$suggestSolution = "ball.W8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXD3.$suggestSolution = "ball.V8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXDV.$suggestSolution = "ball.Y8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXER.$suggestSolution = "ball.V13";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_RXLINK.$suggestSolution = "ball.W13";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD0.$suggestSolution = "ball.AA8";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD1.$suggestSolution = "ball.U9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD2.$suggestSolution = "ball.W9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXD3.$suggestSolution = "ball.AA9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII0_TXEN.$suggestSolution = "ball.Y9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_COL.$suggestSolution = "ball.V14";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_CRS.$suggestSolution = "ball.W14";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD0.$suggestSolution = "ball.W11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD1.$suggestSolution = "ball.V11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD2.$suggestSolution = "ball.AA12";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXD3.$suggestSolution = "ball.Y12";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXDV.$suggestSolution = "ball.W12";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXER.$suggestSolution = "ball.AA13";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_RXLINK.$suggestSolution = "ball.U12";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD0.$suggestSolution = "ball.AA10";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD1.$suggestSolution = "ball.V10";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD2.$suggestSolution = "ball.U10";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXD3.$suggestSolution = "ball.AA11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII1_TXEN.$suggestSolution = "ball.Y11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MR0_CLK.$suggestSolution = "ball.AA7";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MR1_CLK.$suggestSolution = "ball.U11";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MT0_CLK.$suggestSolution = "ball.V9";
enet_icss1.PRU_ICSSG1_MII_G_RT.MII_MT1_CLK.$suggestSolution = "ball.Y10";
Next we run the example on our hardware target and the logs from the application look fine, but we are not able to see any communication via the PHYs:
==========================
MULTIPORT TEST
==========================
Init all peripheral clocks
----------------------------------------------
Enabling clocks!
Open all peripherals
----------------------------------------------
Init configs EnetType:2, InstId :1
----------------------------------------------
icssg1: Open port 1
EnetPhy_bindDriver:1718
icssg1: Open port 2
EnetPhy_bindDriver:1718
PHY 3 is alive
PHY 7 is alive
icssg1: Register async IOCTL callback
icssg1: Register TX timestamp callback
Attach core id 1 on all peripherals
----------------------------------------------
icssg1: Attach core
Create RX tasks
----------------------------------------------
icssg1: Create RX task
icssg1: Waiting for link up...
Enet Multiport Menu:
'T' - Enable timestamp prints
't' - Disable timestamp prints
's' - Print statistics
'r' - Reset statistics
'm' - Show allocated MAC addresses
'd' - Enable dscp based priority mapping
'x' - Stop the test
Icssg_handleLinkUp:3060
icssg1: Port 1 link is up
icssg1: Set port state to 'Forward'
icssg1: Async IOCTL completed
icssg1: Async IOCTL completed
Icssg_handleLinkUp:3060
icssg1: Port 2 link is up
icssg1: Set port state to 'Forward'
icssg1: Async IOCTL completed
icssg1: Async IOCTL completed
icssg1: Open DMA
initQs() txFreePktInfoQ initialized with 8 pkts
icssg1: Set MAC addr: 70:ff:76:1d:92:c1
icssg1: MAC port addr: 70:ff:76:1d:92:c1
We can't see any communication from the target (it should loop back all received frames) but the Link detection etc seems to work. As we looked a bit deeper in the example we set a breakpoint in the EnetUdma_rxCqIsr() function and it is never called.
The check the correct PHY configuration we made a PHY Register Dump right after Startup:
PHY 3 Register Dump Register 0000 is: 2100 Register 0001 is: 7849 Register 0002 is: 2000 Register 0003 is: A131 Register 0004 is: 0181 Register 0005 is: 0000 Register 0006 is: 0004 Register 0007 is: 2001 Register 0008 is: 0000 Register 0009 is: 0020 Register 000A is: 0100 Register 000B is: 040B Register 000C is: 0000 Register 000D is: 0000 Register 000E is: 0000 Register 000F is: 0000 Register 0010 is: 0004 Register 0011 is: 0108 Register 0012 is: 0000 Register 0013 is: 0000 Register 0014 is: 0000 Register 0015 is: 0000 Register 0016 is: 0100 Register 0017 is: 0041 Register 0018 is: 0400 Register 0019 is: C003 Register 001A is: 0000 Register 001B is: 007D Register 001C is: 05EE Register 001D is: 0000 Register 001E is: 0102 Register 0467 is: 00CF Register 0468 is: 2586 PHY 7 Register Dump Register 0000 is: 2100 Register 0001 is: 7849 Register 0002 is: 2000 Register 0003 is: A131 Register 0004 is: 0181 Register 0005 is: 0000 Register 0006 is: 0004 Register 0007 is: 2001 Register 0008 is: 0000 Register 0009 is: 0020 Register 000A is: 0100 Register 000B is: 040B Register 000C is: 0000 Register 000D is: 0000 Register 000E is: 0000 Register 000F is: 0000 Register 0010 is: 0004 Register 0011 is: 0108 Register 0012 is: 0000 Register 0013 is: 0000 Register 0014 is: 0000 Register 0015 is: 0000 Register 0016 is: 0100 Register 0017 is: 0041 Register 0018 is: 0400 Register 0019 is: C007 Register 001A is: 0000 Register 001B is: 007D Register 001C is: 05EE Register 001D is: 0000 Register 001E is: 0102 Register 0467 is: 00DF Register 0468 is: 2186
What is strange to us, is the fact that "Auto-Negotiation" seems to be disabled - it should be enabled via strap pin (see strap latch in register 0x0467).
We made an additional Register Dump after the LinkUp Event and now he seems to get the "Auto-Negotiation" enabled correctly, but still there is no communication possible.:
After LinkUp PHY 3 Register Dump Register 0000 is: 3100 Register 0001 is: 786D Register 0002 is: 2000 Register 0003 is: A131 Register 0004 is: 01E1 Register 0005 is: CDE1 Register 0006 is: 000F Register 0007 is: 2001 Register 0008 is: 0000 Register 0009 is: 0020 Register 000A is: 0100 Register 000B is: 040B Register 000C is: 0000 Register 000D is: 0000 Register 000E is: 0000 Register 000F is: 0000 Register 0010 is: 0015 Register 0011 is: 0108 Register 0012 is: 6400 Register 0013 is: 2800 Register 0014 is: 0000 Register 0015 is: 0000 Register 0016 is: 0100 Register 0017 is: 0041 Register 0018 is: 0400 Register 0019 is: CC03 Register 001A is: 0000 Register 001B is: 007D Register 001C is: 05EE Register 001D is: 0000 Register 001E is: 0102 Register 0467 is: 00CF Register 0468 is: 2586 PHY 7 Register Dump Register 0000 is: 3100 Register 0001 is: 786D Register 0002 is: 2000 Register 0003 is: A131 Register 0004 is: 01E1 Register 0005 is: 45E1 Register 0006 is: 0007 Register 0007 is: 2001 Register 0008 is: 0000 Register 0009 is: 0020 Register 000A is: 0100 Register 000B is: 040B Register 000C is: 0000 Register 000D is: 0000 Register 000E is: 0000 Register 000F is: 0000 Register 0010 is: 0615 Register 0011 is: 0108 Register 0012 is: 6400 Register 0013 is: 2800 Register 0014 is: 0000 Register 0015 is: 0000 Register 0016 is: 0100 Register 0017 is: 0041 Register 0018 is: 0400 Register 0019 is: CC07 Register 001A is: 0000 Register 001B is: 007D Register 001C is: 05EE Register 001D is: 0000 Register 001E is: 0102 Register 0467 is: 00DF Register 0468 is: 2186
Here is another point that confuses us: Why is the Reserved Bit 10 in Register 0x19 set to 1 after LinkUp?
Do you have any hints why communication could not be working and where we could do further investigations?
Best regards
Alex
