Part Number: DS90UB941AS-Q1
Hi together,
We cannot start the ext. timing. and ext. Clock mode.
We already validate the deep physical layer with an high speed differential oscilloscope.
We are using a continuous DSI Clock. May this cause a configuration error? We always see framing errors, when we are read out the 941.
##EXT CLK EXT Timing Mode --- NOT Working
i2cset -y 16 0xc 0x1 0xe #Diasalbe DSI, DSI_Reset,Digial_Reset1
sleep 1
i2cset -y 16 0xc 0x1e 0x1 #PORT0_SEL =0-> Write to Port0
i2cset -y 16 0xc 0x4f 0x8c #DSI_cont_clk 4 Lanes
i2cset -y 16 0xc 0x5b 0x4 #Auto-Detect FPD-Link III mode
i2cset -y 16 0xc 0x40 0x4 #ind registers Port 0
i2cset -y 16 0xc 0x41 0x21 #ind register 0x21
i2cset -y 16 0xc 0x42 0x60 #VS active low, HS active lo
i2cset -y 16 0xc 0x40 0x4 #ind registers Port 0
i2cset -y 16 0xc 0x41 0x5 #ind register 0x5
i2cset -y 16 0xc 0x42 0x14 #TSKIP_CNT Reset=0x3A, amount of data that will be ignored at end of transmission detection
i2cset -y 16 0xc 0x66 0x00 #PATGEN_ID -> 0x0
i2cset -y 16 0xc 0x67 0x00 # Reset value Red = 0
i2cset -y 16 0xc 0x66 0x01 #PATGEN_ID -> 0x1
i2cset -y 16 0xc 0x67 0x00 # Reset value Green = 0
i2cset -y 16 0xc 0x66 0x02 #PATGEN_ID -> 0x2
i2cset -y 16 0xc 0x67 0x00 # Reset value blue = 0
i2cset -y 16 0xc 0x66 0x03 #PGCDC1 --> PGCDC1
i2cset -y 16 0xc 0x67 0x03 # int. PCLK = 66.6MHz
i2cset -y 16 0xc 0x66 0x04 #PATGEN_ID -> PGTFS1
i2cset -y 16 0xc 0x67 0x70 # Horizontal Width default is 48h
i2cset -y 16 0xc 0x66 0x05 #PATGEN_ID -> PGTFS2
i2cset -y 16 0xc 0x67 0xe6 # Total vertical Width lsb=eh (5h); horizonatl msb=6h (4h)
i2cset -y 16 0xc 0x66 0x06 #PATGEN_ID -> PCTFS3
i2cset -y 16 0xc 0x67 0x2e # Total vertical Width msb= 2eh (1eh)
i2cset -y 16 0xc 0x66 0x07 #PATGEN_ID -> PGAFS1
i2cset -y 16 0xc 0x67 0x00 # Active Horizontal Width lsb(8)= 00 (20h)
i2cset -y 16 0xc 0x66 0x08 #PATGEN_ID -> PGAFS2
i2cset -y 16 0xc 0x67 0x05 # Active Vertical Width (lsb4)= 0(0) Active Horizontal Width (msb4)=5h(3h)
i2cset -y 16 0xc 0x66 0x09 #PATGEN_ID -> PGAFS3
i2cset -y 16 0xc 0x67 0x2d # Active Vertical Width (msb8)=2Dh(1Eh)
i2cset -y 16 0xc 0x66 0x0a #PATGEN_ID -> PGHSW
i2cset -y 16 0xc 0x67 0x50 # Horizontal Sync Width 50h(Ah)
i2cset -y 16 0xc 0x66 0x0b #PATGEN_ID -> PGVSW
i2cset -y 16 0xc 0x67 0x05 # Vertical Sync Width 05h(2h)
i2cset -y 16 0xc 0x66 0x0c #PATGEN_ID -> PGHBP
i2cset -y 16 0xc 0x67 0xd8 # Horizontal Back Porch Width =d8h (Ah)
i2cset -y 16 0xc 0x66 0x0d #PATGEN_ID -> PGVBP
i2cset -y 16 0xc 0x67 0x16 # Vertical back Porch Width 16h(2h)
i2cset -y 16 0xc 0x66 0x0e #PATGEN_ID -> PBSC
i2cset -y 16 0xc 0x67 0x00 # Horizontal Sync Disable =0(0) ; Vertical Sync Polarity=0(1)# in int. timing mode inverting; ext. timing mode no effect
i2cset -y 16 0xc 0x66 0x0f #PATGEN_ID -> PGFT
i2cset -y 16 0xc 0x67 0x1e # Frame Time 1e(1e)
i2cset -y 16 0xc 0x66 0x10 #PATGEN_ID -> PGTSC
i2cset -y 16 0xc 0x67 0x0e # PATGEN_TSLOT (0xe)0xC number of enabled timeslots
i2cset -y 16 0xc 0x66 0x11 #PATGEN_ID -> PGSO1
i2cset -y 16 0xc 0x67 0x21 # Timslot source default
i2cset -y 16 0xc 0x66 0x12 #PATGEN_ID -> PGTSO2
i2cset -y 16 0xc 0x67 0x43 # Timslot source default
i2cset -y 16 0xc 0x66 0x13 #PATGEN_ID -> PGTSO3
i2cset -y 16 0xc 0x67 0x65 # Timslot source default
i2cset -y 16 0xc 0x66 0x14 #PATGEN_ID -> PGTSO4
i2cset -y 16 0xc 0x67 0x87 # Timslot source default
i2cset -y 16 0xc 0x66 0x15 #PATGEN_ID -> PGTSO5
i2cset -y 16 0xc 0x67 0xa9 # Timslot source default
i2cset -y 16 0xc 0x66 0x16 #PATGEN_ID -> PGTSO6
i2cset -y 16 0xc 0x67 0xcb # Timslot source default
i2cset -y 16 0xc 0x66 0x17 #PATGEN_ID -> PGTSO7
i2cset -y 16 0xc 0x67 0xed # Timslot source default
i2cset -y 16 0xc 0x66 0x18 #PATGEN_ID -> PGTSO8
i2cset -y 16 0xc 0x67 0x0f # Timslot source default
i2cset -y 16 0xc 0x66 0x19 #PATGEN_ID ->PGBE
i2cset -y 16 0xc 0x67 0x00 # PATGEN_BIST_ERRS clear on read default
i2cset -y 16 0xc 0x66 0x1a #PATGEN_ID ->PGCDC2
i2cset -y 16 0xc 0x67 0x01 # Clock Divider value M is default value 1h
i2cset -y 16 0xc 0x65 0x0 #ext. timing,
i2cset -y 16 0xc 0x64 0xc1 #change Fixed pattern to 1100(0001); enable Pattern Generator
i2cset -y 16 0xc 0x0 0x0 #SER_ID is from IDX Pin
# start debugging
i2cset -y 16 0xc 0x4 0x20 #GENDERAL_CFG2: Clear CRC Error Counter
sleep .1
i2cset -y 16 0xc 0x4 0x0 #GENDERAL_CFG2: "Clear CRC Error Counter" off
sleep 1
val=`i2cget -y 16 0xc 0xc`
echo "GENERAL_STS Register (Address = 0xC): ${val}"
val=`i2cget -y 16 0xc 0x1f`
echo "FREQ_COUNTER Register (Address = 0x1F): ${val}"
val=`i2cget -y 16 0xc 0x50`
echo "BRIDGE_STS Register (Address = 0x50): ${val}"
val=`i2cget -y 16 0xc 0x5a`
echo "DUAL_STS_DUAL_STS_P1 Register (Address = 0x5A): ${val}"
val=`i2cget -y 16 0xc 0x5f`
echo "DSI_FREQ_DSI_FREQ_P1 Register (Address = 0x5F): ${val}"
i2cset -y 16 0xc 0x40 0x4
i2cset -y 16 0xc 0x41 0x6
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_LP_POLARITY Register (Offset = 0x6): ${val}"
i2cset -y 16 0xc 0x41 0xf
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_STATUS Register (Offset = 0xF): ${val}"
i2cset -y 16 0xc 0x41 0x10
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_DLANE0_ERR Register (Offset = 0x10): ${val}"
i2cset -y 16 0xc 0x41 0x11
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_DLANE1_ERR Register (Offset = 0x11): ${val}"
i2cset -y 16 0xc 0x41 0x12
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_DLANE2_ERR Register (Offset = 0x12): ${val}"
i2cset -y 16 0xc 0x41 0x13
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_DLANE3_ERR Register (Offset = 0x13): ${val}"
i2cset -y 16 0xc 0x41 0x14
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_ERR_CLK_LANE Register (Offset = 0x14): ${val}"
i2cset -y 16 0xc 0x41 0x15
val=`i2cget -y 16 0xc 0x42`
echo "DPHY_SYNC_STS Register (Offset = 0x15): ${val}"
i2cset -y 16 0xc 0x41 0x22
val=`i2cget -y 16 0xc 0x42`
echo "DSI_ERR_CFG_0 Register (Offset = 0x22): ${val}"
i2cset -y 16 0xc 0x41 0x23
val=`i2cget -y 16 0xc 0x42`
echo "DSI_ERR_CFG_1 Register (Offset = 0x23): ${val}"
i2cset -y 16 0xc 0x41 0x28
val=`i2cget -y 16 0xc 0x42`
echo "DSI_STATUS Register (Offset = 0x28): ${val}"
i2cset -y 16 0xc 0x41 0x2a
val=`i2cget -y 16 0xc 0x42`
echo "DSI_VC_DTYPE Register (Offset = 0x2A): ${val}"
i2cset -y 16 0xc 0x41 0x2b
val=`i2cget -y 16 0xc 0x42`
echo "DSI_ERR_RPT_0 Register (Offset = 0x2B): ${val}"
i2cset -y 16 0xc 0x41 0x2c
val=`i2cget -y 16 0xc 0x42`
echo "DSI_ERR_RPT_1 Register (Offset = 0x2C): ${val}"
i2cset -y 16 0xc 0x41 0x2d
val=`i2cget -y 16 0xc 0x42`
echo "DSI_ERR_RPT_2 Register (Offset = 0x2D): ${val}"
i2cset -y 16 0xc 0x41 0x3a
val=`i2cget -y 16 0xc 0x42`
echo "DSI_PCLK_DIV_M Register (Offset = 0x3A): ${val}"
i2cset -y 16 0xc 0x41 0x3b
val=`i2cget -y 16 0xc 0x42`
echo "DSI_PCLK_DIV_N Register (Offset = 0x3B): ${val}"
When we change in line 68 to:
i2cset -y 16 0xc 0x65 0xc #ext. clk, int. timing
Then we see an Test pattern on screen with int timing.
Is it possible, that a continuous clk prevent the application processor to configure with the 941?
Do you see an other error in our script?
Thanks for all answers
Ulrich
