I am testing loopback for LVDS SerDes interface in my FPGA (the SerDes is using LVDS standard). The FPGA will output Tx+/Tx- and Rx+/Rx- and I want to loopback Tx+ to Rx+ and Tx- to Rx- to test the verilog. I plan to use the DS90LV804 to buffer the signals from the FPGA. Would this be the correct connection for the purpose of this test?
