Other Parts Discussed in Thread: SN65LV1023A
Hello,
I am trying to use a Tektronix MSO68B oscilloscope to perform jitter analysis on the differential serial data between the SN65LV1023A and SN65LV1224B. The oscilloscope actually recovers the clock from the serial data with its built in software features. I want to configure the oscilloscope PLL in such a way that it is well matched to the PLL inside the SN65LV1224B. Can you provide some suggested values? I think the most valuable would be the loop bandwidth and if it needs to be adjusted depending on the data rate? We are most likely clocking both ICs with a minimum TCLK and REFCLK of 10 MHz but that can be changed. Below is an image of the clock recovery settings:
Thank you in advance for your time. Kind regards,
