SN65DSI86: SOFT_RESET

Christian

What is the exact issue you are seeing when the DSI86 failed? Does the DSI86 color bar function still work in this failed state? 

If you set the soft_reset bit, does the failed condition go away?

Can you also share your schematic?

Thanks

David

David,

that would be then the third time, I'm sharing the schematics. TI already did a review. Anyway, the preceding issue is covered in the question handled in "SN65DSI86: SN65DSI86".

What I want know is to understand, how to properly perform a soft_reset...  The issue I'm still experiencing is, that from time to time the system remains in failing the link training with the display. What I never tried so far is to perform a soft_reset at the correct position of the init sequence.

Thanks

Christian

Christian

I would go with this sequence,

1. DSI86 CSR configuration, do not enable DP link training and video stream yet

2. Set DSI86 SOFT_RESET bit

3. Wait 10ms

4. Enable DSI CLK in HS mode only 

5. Enable DSI86 DP_PLL_EN bit

6. Wait 10ms

7. Check DP_PLL_LOCK bit and make sure it is set

8. Enable DP Link Training

9. Make sure link training is successful

10. Send DSI video data

11. Enable DSI86 video stream bit

Do you have a way to provide an external clock to the DSI86 reference clock input? I want to check and see if the problem would still happen with an external reference clock.

Thanks

David

David

thanks for this procedure, I'll try this out!

Actually not having an external refclk was one of the first failure happened in the first design loop (the other was not pulling TEST2-Pin as our display does not support ASSR). I was not able to get the DSI-Clock to one of the required frequencies.

What remained until my last change was, that the screen remained dark after changing the virtual terminal from text to graphic (using chvt) which basically disables and re-enables the whole DRM chain. This looked could be fixed by performing the soft_reset once the error flag DPTL_DATA_UNDERRUN_ERR is set.

Now the remaining problem is, that the init sequence fails earlier.

Thanks,

Christian

Christian

So if I understand correctly, you are already using the REF CLOCK as the input clock source instead the DSI CLK? 

I will try the sequence I sent earlier and see if it will solve your issue.

Thanks

David

David

Yes, we've added a 27Mhz oscillator to the second design version which is currently in use (see below the cutout).

Thanks,

Christian