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DP83867IR: clk_out(XI input clock) is not 25Mhz

GukHyun Lee
Intellectual 260 points

Part Number: DP83867IR

Hi, experts.

I made a custom board with dp83867irpap.

I have a problem with ping with a PC.

When I probe clk_out pin, which is synchronous to XI input clock, I got around 2kHz.

I thought this is wrong and the clk_out pin should be 25 MHz.

I checked the crystal part is for 25MHz.

Both XI and XO are around 2kHz..

I couldn't find why the crystal out (XI) is not 25MHz...

Could you comment for me?

Really thanks.

  • 0
    TI__Mastermind 19250 points

    Hi GukHyun,

    Can you please measure the CLK_OUT pin after removing the stubs/probes on XI/XO?
    Having any additional probes on XI/XO will affect the clock frequency and it is better we eliminate this variable before looking further into this issue.

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    Intellectual 260 points

    Hi, I measured the CLK_OUT pin after removing other porbes.

    The result is the picture upper.

    I have a question

    According to datasheet, VDDIO can be 1.8V, 2.5V and 3.3V.

    How can the dp83867 be configured as a specific voltage among them?

    Is it ok to select one option without any configuration?

  • 0 in reply to GukHyun Lee
    TI__Mastermind 19250 points

    Hi GukHyun,

    We need not set any configuration/register for different levels of VDDIO. The VDDIO level is auto-detected by the PHY.

    On the failure, is this failure observed part-to-part or seen across all the boards and parts?

    Can you please share the schematic with me?

    Along with the schematic, can you please share the following waveforms overlapped on each other?

    1. Power supplies VDDA, VDD1P0, VDDIO, VDD1P8V
    2. RESET_N 

    If external VDD1P8V is not used, is it left unconnected?

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    Intellectual 260 points

    Hi, Gokul.

    I solved it from changing the Load cap.

    Thank you for your comment.