SN65DSI83: Uboot Display dirver

Hi Kaushal,

First, please ensure that you are setting your registers appropriately based on the display's datasheet. For your convenience, I have included some links below: 

Step-by-step Configuration guide: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation

Register Configuration Tool: https://www.ti.com/tool/DSI-TUNER

Second, please refer to section 7.4.2 of the DSI83 datasheet to ensure that you are following the correct initialization sequence for this application.

Lastly, try utilizing the test pattern function again and see if the same result occurs.

Thanks,

Zach

Hi Zach,

Display is working fine with the I2C register configuration in kernel but the same I2C configuration is not working in Uboot.

I followed the same power sequence provided in datasheet. PFB image.

Their is only one I2C register configuration is different 0x0A in kernel its value is 0x85 and in uboot it is 0x05

0x85 hex = 10000101 and 0x05 = 00000101 we can see from 0x0A register table 7th bit is read only bit.

It is PLL_EN status bit which is enable as we can see 0x0D register is 0x01.

Could you please tell us the reason of this contradiction.

Regards,

Kaushal Verma

Hi Kaushal,

The problem seems to be sourced from the differences in the working kernel vs the Uboot implementation. 

I would recommend determining how the Uboot implementation is different from the working kernel.

Thanks,

Zach 

Hi Zach,

Could you please confirm, we need MIPI signals to create test pattern.

As per my knowledge we don't need any MIPI data to print test pattern just need to write 0x3C register to 0x10.

Once I get test pattern then I will further dig to connect working SN65DSI83 bridge to MIPI data to print splash screen.

NOTE: I did changes to parse display timing parameters to mipi_dsi driver.

Regards,

Kaushal Verma

Kaushal,

The test pattern does not need the MIPI DSI data. (see 7.3.3 LVDS Pattern Generation of the data sheet)

Assuming the display you are using is compatible with the DSI83 device, if you set the device registers correctly based on the display's datasheet then you should get a good test pattern.

Thanks,

Zach

Hi Zach,

The I2C register configuration of SN65DSI83 is same in both working kernel and Uboot Implementation except 0X0A register. 

Kindly see above mail for the detail information.

Could you please suggest the cause of contradicting in my case "0x0D register and 7th bit of 0x0A register represent the status of 0x0D register"

Regards,

Kaushal Verma

Hi Kaushal,

The problem seems to be with Uboot's ability to interface with the DSI83. 

I recommend looking through Uboot documentation to see how it is interfacing with the device differently than the working kernel.

Thanks,

Zach

Zach,

Understood, I found the difference in Kernel and Uboot. When I enable 0x0D register It automatically update 0x0A register in Kernel. But It didn't change in Uboot.

Could you please look into this.

Regards,

Kaushal Verma

Kaushal,

I am unsure of Uboot's implementation and why it is not allowing 0x0A to update.

I recommend using the working Kernel in your application instead of Uboot.

Thanks,

Zach

Zach,

I need to develop uboot display driver to show splash screen on display. 

When I turn on the device I couldn't see any thing for 13 sec kernel starting time. 

that's why I am developing the driver.

Regards,

Kaushal Verma

Kaushal

Are you using the MIPI DSI or the Ref clock as your clock source? Can you please probe the clock and the DSI83 EN pin to make sure the clock is up and running before the EN goes from low to high?

Thanks

David

Kaushal

Can you check with the MIPI source vendor to see how the MIPI clock is being configured?

Thanks

David

Kaushal,

Is there anything else that I can help you with on this? 

If not we can close this ticket.

Thanks,

Zach

Hi Zach,

Could you please tell me the procedure to put SN65DSI83 MIPI to LVDS convertor in LP11 state.

Please tell me the procedure to verify weather it is in LP11 mode or Normal mode.

Thanks,

Kaushal Verma

Hello Kaushal,

When the MIPI inputs are driven to LP11 this means that both P and N pairs of all MIPI DSI differential pairs are driven to single ended high ~1.2V.

This can be verified with an oscilloscope by probing the P and N pairs of the MIPI DSI.

Thanks,
Zach

Hi Zach,

Understood your point on how to put SN65DSI83 in LP11 mode hardware wise but could you please help me understand how to put it in LP11 mode using software. And how to change from LP11 mode to normal mode.

We don't have oscilloscope for now is there any way to verify the mode other then using oscilloscope.

Thanks,

Kaushal Verma

Kaushal,

LP11 mode is driven by what you are using for the source of the DSI signal and not by the DSI84 device.

Here is a website that can help you understand how the transition occurs between LP11 and HS modes: https://circuitcellar.com/resources/quickbits/mipi-display-serial-interface/

Thanks,
Zach

Hi Zach,

Thanks for the support.

We are getting 1049 MHz in MIPI DSI and I used clock divider 14 to make it around 76 MHz in LVDS and could see the proper test pattern in LVDS in Uboot with developed driver.

When I disabled the test pattern I could see the fluctuating splash screen.

As per my observation the issue is 0x12 register of SN65DSI83.

CHA_DSI_CLK_RANGE
This field specifies the DSI clock frequency range in 5-MHz increments for
the DSI channel A clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
…
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved

We can use the DSI clock upto 500 MHz only and in our case it is 1049 MHz.

Could you please provide your inputs here and help me to debug this issue.

Regards,

Kaushal Verma 

Hi Kaushal,

Have you checked with the MIPI source vendor to see how the MIPI clock is being configured as suggested above?

Thanks,

Zach

Hi Zach

I checked with NXP and I am not getting any support on how to change Uboot MIPI DSI clock. It is 1049 MHz by default so I am setting 0x0b register DSI_CLK_DIVIDER 14 to get clock around 76 MHz but the splash screen is fluctuating because I cannot set CHA_DSI_CLK_RANGE more then 500 MHz.

Could you please help me set MIPI DSI clock below 500 MHz in uboot or if you have any workaround to set CHA_DSI_CLK_RANGE for 1049 MHz.

Thanks for your help.

Regards,

Kaushal Verma