• State TI Thinks Resolved
  • Locked Locked
  • Replies 52 replies
  • Answers 1 answer
  • Subscribers 35 subscribers
  • Views 1569 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO3130: Port not working - Debug

mbbrouwer
Expert 3650 points
Part Number: XIO3130

Hi there,

Customer is having an issue with the XIO3130.

 

Here is the issue:

 

Although the device seems properly strapped, and devices are present on downstream ports 1 and 2, customer is only seeing activity on downstream port 2.

If they scan the PCI bus, they see the device itself, all its downstream ports, as well as the device on downstream port 2, but nothing on downstream port 1 (no reference clock is present – see below)

Even though downstream port 3 is not enabled, there is a reference clock present (100Mhz – see below)

 

Here is a little more detail:

 

DN1_DPSTRAP = 3.3V

GPIO[0] = 418 mV (4.7K Resistor)

GPIO[1] = 0V

GPIO[2] = 3.3V

DN1_REFCLKO: No activity

 

DN2_DPSTRAP = 3.3V

GPIO[4] = 426 mV (4.7K Resistor)

GPIO[5] = 0V

GPIO[6] = 3.3V

DN2_REFCLKO: 100 MHz clock

 

DN3_DPSTRAP = 0V

GPIO[8] = 3.3V

DN3_REFCLKO: 100 MHz clock

 

 

Do you think somebody could help explain this behavior? Anything missed in the datasheet?

Thanks!

  • 0 in reply to Nicholaus_Malone
    Intellectual 350 points

    Hi Nicholaus,

    I'm sorry for the delay in responding - I've got a couple of couple of issues that have taken higher priority given our apparent "work-around" for this issue.

    To answer your question: No, I still have no explanation for the difference in behavior between the two downstream ports. All our attempts at examining the communication on the PCIe bus have failed so far - we just don't have the equipment to probe the bus and see what is happening.

    This is still an active issue for me - I am just trying to clear a couple of other issues so I can focus more closely on it.

    If I have any questions for you or make any observations I think are important I will let you know immediately.

    Thanks for checking in.

    Best regards,

    Steve

  • 0 in reply to Steven DuTemple
    TI__Mastermind 27925 points

    Hi Steve,

    Alright.  Thanks for the updates.   My latest question is asking if the EEPROM image is different between the 3 boards, which doesn't require the PCIe bus, but we can revisit that when you return.

    Regards,

    Nicholaus