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TFP401 clock distribution

Other Parts Discussed in Thread: TFP401, TFP403

Please help my customer with the following (should I recommend the use of a buffer?)

Question about the TFP401. I will be using the TFP401 in a Dual DVI receiver mode. In the "Digital Visual Interface FAQ", question #10, is says to distribute the DVI clock to both receivers. Does TI have a recommended method to do this? Should a 1:2 fanout chip be used? Is there a part that TI recommends?

Thanks, Saeb

  • Hello Saeb,

     

    The TI's solution for a DVI dual link is to use two transmitters and two receivers.

    TFP410----------------TFP401/TFP403

    TFP410----------------TFP410/TFP403

    Regards.

  • I am re-stating the issue:

    My current design uses the TFP401 as dual DVI receivers.  According to the Digital Visual Interface FAQ from TI, question 10 states:

     

    10. How do I implement a dual link receiver using the TFP401?

     

    The TFP401 was not designed to function as a part of a dual link receiver. With dual link DVI, only 1 clock is transmitted with the 6 data channels. A single link receiver will deskew the 3 data channels it receives and output these with the ODCK signal to clock the output data into a register in the next device. To use 2 single link receivers for dual link, the DVI clock must be distributed to both receivers. The outputs of the 2 receivers must be recovered using their appropriate ODCK. Any skew between the receivers removed, and converted to a single clock domain.           

     

     

    My question is how should the clock be distributed to both receivers?

     Is an external 1 to 2 buffer needed? 

    Is there a TI recommended part for this?

     

    Thanks, Saeb

     

  • Saeb, you might consider using a dual-routed clock trace with a series resistor.

    Thanks,
    RE

  • Hi Saeb,

    I work on a project similar to yours : a solution based on the use of 2 TFP401 in order to do a dual link receiver. Does this configuration work on your board ?

    Could you give me layout guidelines, clock distribution reference ?

    Best regards,

    Laurent.