TLK2711-SP: Regarding the TXCLK provision for TLK2711

Maitry Khambhati

Part Number: TLK2711-SP
Other Parts Discussed in Thread: LMK04803

Hello support team,

We are planning to use the Clock synthesizer(LMK series) for the TXCLK provision of 110 MHz to TLK2711 SERDES IC. As per datasheet and calculations, found out that the required RMS jitter performance is < 450 femto sec. But my question is about the integrated BW. How to select the Integrated BW criteria on which jitter performance needs to be verified? Can you please guide on the same?

As all LMK series clock synthesizer has given their characteristics on jitter is 111 femto sec(approx) with the integrated BW of 12 KHz to 20 MHz.

over 3 years ago

0 Drew Miller1 over 3 years ago

TI__Mastermind 36443 points

Hi,

The datasheet states that the PLL is sensitive to noise in the range of 300 KHz to 3 MHz. Based on this, the LMK series clock would work well in this application. Some additional details regarding the TLK2711 PLL bandwidth can be found in the post below.

https://e2e.ti.com/support/data-converters-group/data-converters---internal/f/data-converters---internal-forum/140548/tlk2711-pll-question

Thanks,

Drew

0 Maitry Khambhati over 3 years ago in reply to Drew Miller1

Intellectual 450 points

Hi,

Thank you for your response.

Can you please resend the above link? As above link is providing error of page not found?

As with LMK04803 clock synthesizer with 110 MHz output , we will be able to get the jitter performance of approx. 140 fsec. (this we have verified using pllatium tool simulation) within Integration BW for 12 KHz to 20 MHz. So, it will be working well with TLK2711 with LVCMOS input.

Is there anything that we need to take care for using LMK04803 with TLK2711 IC for TXCLK , Kindly request you to provide your support and guidance.

0 Drew Miller1 over 3 years ago in reply to Maitry Khambhati

TI__Mastermind 36443 points

Hi,

Regarding the other link, I actually just realized it is to an internal thread. The following is an excerpt from that thread.

"The TLK2711 Jitter transfer from TXCLK to TX is flat up to about 1Mhz, then peaks at +3-4db around 2mzh, and rolls off at 20db/decade above 2Mhz.

Jitter in the 1-3mhz range is the most detrimental to performance."

The primary design concerns for TXCLK are ensuring that input electrical characteristics and clocking timing requirements are met.

Thanks,

Drew

0 Maitry Khambhati over 3 years ago in reply to Drew Miller1

Intellectual 450 points

Hi,

Thank you for the response.

I have verified the LMK04803 jitter performance with commercial available crystek VCXO for the 100 MHz LVCMOS signal for the integration range of 300 KHz to 3 MHz, which is < 100 femto sec for this particular integration range.

And for the integration BW of 12 KHz to 20 MHz, it is< 200 femto sec. So, I think this would be a suitable solution for providing TXCLK for TLK2711.

+1 Drew Miller1 over 3 years ago in reply to Maitry Khambhati

TI__Mastermind 36443 points

Hi,

Based on everything you have described, I believe the LMK04803 would be suitable for this application.

Thanks,
Drew

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TLK2711-SP: Regarding the TXCLK provision for TLK2711