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DS250DF230: clock low period (Slave mode)

Part Number: DS250DF230

Hi,

The customer wants to combine an MSP430F5419AIPZR (master) with a DS250DF230ZLSR (slave) for I2C communication.
From the thread below, we can read Clock low period (min) = 1.3 us (400kHz class).

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/891563/ds250df230-smbus-switching-characteristics-slave-mode?tisearch=e2e-sitesearch&keymatch=DS250DF230#

1. Is the DS250DF230 ”clock low period" rounded up to 1.3us?
2. Can they use the DS250DF230 "clock low period" at 1.28us?
3. Is there a timing chart with tlow, tSU_DAT, etc.?

Best Regards,

Nishie

  • Hi,

    Please see SMBus parameters table below applicable to the TI retimers. I would not expect issue with 1.28us T_LOW; there should be timing margin. At the same time we cannot guarantee it.

    TABLE: SERIAL MANAGEMENT BUS INTERFACE AC TIMING SPECIFICATIONS

    Symbol

    Parameter

    Condition

    Min

    Typ

    Max

    Units

    FSMB

     

    Bus Operating Frequency

    ENSMB = VDD (Slave Mode)

    100

     

    400

    kHz

    TBUF

    Bus Free Time Between Stop and Start Condition

     

    1.3

     

     

    μs

    THD:STA

    Hold time after (Repeated) Start Condition. After this period, the first clock is generated.

     

    0.6

     

     

    μs

    TSU:STA

    Repeated Start Condition Setup Time

     

    0.6

     

     

    μs

    TSU:STO

    Stop Condition Setup Time

     

    0.6

     

     

    μs

    THD:DAT

    Data Hold Time

     

    0

     

     

    ns

    TSU:DAT

    Data Setup Time

     

    100

     

     

    ns

    TLOW

    Clock Low Period

     

    1.3

     

     

    μs

    THIGH

    Clock High Period

     

    0.6

     

    50

    μs

    tF

    Clock/Data Fall Time

     

     

     

    300

    ns

    tR

    Clock/Data Rise Time

     

     

     

    300

    ns

     Thanks,

    Rodrigo Natal

  • Hi Rodrigo Natal-san,

    Thanks for the answer.

    We will answer the customer about No. 1 and No. 2.
    Regarding No. 3, is it correct to assume that the relevant part of each parameter is the same as the timing chart of I2C?

    Best Regards,

    Nishie

  • Yes, your assumption is correct.

    Thanks,

    Rodrigo Natal