DP83TD510E: What registers control the Non-Delay Mode or Integrated Delay Mode of the RGMII-10 interface

I need to set the RGMII INPUT TIMING (10M) to Non-Delay mode to manage the interface timing against another circuit which outputs data on the clock edge +-1ns. With the +-4ns setup/hold requirements this is not possible in the design i am doing, 60cm wires is not feasible. 

Can anyone point me to the registers that control this setting.

I am guessing the interface is reused in other PHY ICs but I am unsure where to look.

Regards