DS125DF410: Relationship of VCO and Retimer/CDR

Hi,

I see how this block diagram might be confusing. I'm including below the block diagram for another TI retimer, the DS250DF410, which uses the same architecture.

• There are two key functions implemented by the retimer, the clock and data recovery (CDR) and the sampling
• The retimer recovers the clock from the input data using PLL functionality to lock the VCO to a specific frequency
• Subsequently this recovered clock from CDR is used to clock the digital sampling logic to effective retime the input data, outputting a lower jitter version of it

As far as we know, CDR should be a standalone function with its own set of circuitry including an internal VCO.So the VCO block shown on the block diagram should not be part of the CDR function. Is our understanding correct? If so, can you let us know how the two relate to each other?

• The VCO+CDR together are the phase and frequency lock acquisition system. There is only one VCO per retimer channel.
• For more education on CDRs I would recommend to check out my CDR TIPL video. See link below
• https://training.ti.com/what-is-clock-and-data-recovery?context=1139747-1138099-1139711-1147427

 For example, when we change the VCO divider value (bit 6:4 of register 0x18) manually, will the CDR function for the input signals be affected?

• The user does not need to manually configure the VCO
• The user simply specifies the data rate that the CDR will attempt to lock to along with the CDR divider ratio. By default the retimer assumes divide by 1 ratio. The user has the option to force divide by 2 or divide by 4 ratio

Thanks,

Rodrigo Natal