DS160PR421: DS160PR421RUAR

Hi Francis,

Could you clarify the values listed?  Does "0" mean "L0" or does "1K" mean L0.  

LEVEL SETTINGS
L0 - 1 kΩ to GND
L1 - 13 kΩ to GND
L2 - 59 kΩ to GND
L3 -  F (Float)

Regards,

Nicholaus

1) SEL = 1K to GND as default and driven by external controller.

2) RX_DET = 1K to GND

3) PD = 1K to GND

4) MODE = 1K to GND

5) GAIN = 1K to GND

6) EQ0 = 1K to GND

7) EQ1 = 1K to GND

Yes, 1K is L0 for gain equalization in level setting.

Thanks

Francis 

Hi Francis,

1) SEL = Low - Port A selected by default and driven by external controller.

2) RX_DET = L0 - Rx Detect force enabled

3) PD = Low = Power-up, normal operation for all channels

4) MODE = L0 - Pin Mode

5) GAIN = L0 - -4.2dB DC Gain

6) EQ0 = L0 - ~0dB

7) EQ1 = L0 - ~0dB

One thing that I recommend changing is the GAIN pin from L0 to L3 (floating) so that the DC gain is 0dB.  Secondly, the only thing I can imagine that would cause no output is if the SEL pin is actually being driven high by the external controller.  Can you confirm that the SEL pin is actually 0V?

Regards,

Nicholaus

HI Nick,

Yes, SEL is 0V.
Let me set the gain to L3 with both EQ0 ad EQ1 floating.

-Francis

EQ0 and EQ1 = L0

GAIN = L3 floating

Hi Francis,

Can you clarify something?   You said "Data is captured at RXA, but there is no output data which is connected to another DS160PR421."

Is it the 1st MUX or the 2nd MUX that is not outputting data?   Do they both have the same configuration?

Maybe you could share your schematic?  I will send you a private message if you wish to keep it confidential.

Regards,

Nicholaus

Hi Nick,

It is the 1st MUX not having output.

Both is in the same configuration for active MUX (not PCIe).

Please, send a private message, and I share the schematics

Thanks

Francis

Please, see private message. Thanks

Hi Francis,

A colleague and I looked at your schematic and don't see any issues, but one thing that came to mind was that the pin-mode values are sampled at power-up.  So, is the SEL pin a stable 0V during the power-up sequence of the mux?

Regards,

Nicholaus

Hi Nick,

The SEL is driven by I2C expander PCAL6524 which has all IO configured as input during power-on until SW coming to drive it, so SEL is low by pull-down resister during power-on-sequence; however, what is SEL effecting the mode set during power-on-sequence?

Thanks

Francis

Hi Francis, 

Interesting, thank you for the information.  I will let the appropriate people know.

Regards,

Nicholaus