SN65DSI84: questions of SN65DSI84

Jimmy Lai

Expert 6845 points

Part Number: SN65DSI84

Dear Team,

The LCM panel support the following input timing.

What is the input timing of the sn65dsi84 corresponding to the following LVDS timings?

I have some other questions:

1.After register setting, the value of register 0xE5 is 0x1, is it OK?

2.How can I check the video data stream sent to sn65dsi84 is OK?

3.In chapter7.6 of sn65dsi84 spec, description of register 0x0D, does it mean mipi PHY clock must be enabled before PLL is enabled?

4.I used Oscilloscope to measure the input clock and mipi data for LCD, but the result was not that good to see, how can I measure it better?

Platform: Ambarella CV25 SoC
System: Linux
Bridge IC: SN65DSI84

Many Thanks,

Jimmy

over 3 years ago

0 Zach Dryer over 3 years ago

TI__Genius 13310 points

Hey Jimmy,

1. Please start by watching this video: https://training.ti.com/configuring-sn65dsi85-dual-channel-dsi-dual-link-lvds-operation. 0xE5 is an error register and is set whenever the PLL lock status becomes unlocked.

2. First, I would recommend verifying that you are setting the registers to support your display specifications.

Second, I would recommend verifying that you are following the initialization sequence Table 2 of the DSI84.

Third, I would recommend setting up the test pattern on the device to verify that you are getting an LVDS signal out that will meet display specifications.

3. DSI MIPI CLK is enabled before PLL_EN. Please see this FAQ for an illustration: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85.

4. What is the bandwidth of the scope that you are using? Please follow the recommendations above and if there are still issues you can send Oscope captures of the EN signal, DSI - CLK, DSI - Data and I2C - SCL.

Thanks,

Zach

0 Zach Dryer over 2 years ago in reply to Zach Dryer

TI__Genius 13310 points

Hey Jimmy,

I wanted to follow up and see if you had any more questions regarding the answer given above.

If you are satisfied with the answer, please click the "This resolved my issue" button on this thread.

Thanks,

Zach

0 Jimmy Lai over 2 years ago in reply to Zach Dryer

TI__Expert 6845 points

Hi Zach,

Thanks for your great support always!

1. Provide the layout point to measure the MIPI data lane and clock.

2. How to check EN pin in LVDS-DE mode?

3. What is the value for the 0x12 register of SN65DSI84 when DSI PHY clock=854MHz?

Many Thanks,

Jimmy

0 Zach Dryer over 2 years ago in reply to Jimmy Lai

TI__Genius 13310 points

Hi Jimmy,

With which product package are you working? You should be able to use an oscilloscope on your PCB to monitor the MIPI data, MIPI clock and EN but the method differs based on PCB layout. The pin layout of these signals is given in the product's datasheet.

3. Per the datasheet, MIPI® D-PHY Channel A Clock Lane operates up to 500 MHz. Please use a clock frequency that is within spec. The DSI Tuner can help you calculate your suggested DSI CLK.

Thanks,

Zach

0 Zach Dryer over 2 years ago in reply to Zach Dryer

TI__Genius 13310 points

Hi,

Did you have any other questions?

If not, please click on the "this resolved my issue" button to close this thread.

Thank you,

Zach

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SN65DSI84: questions of SN65DSI84