DP83869HM: Updated BDSL file?

Hi Marvin,

Allow me to consult the team on this and let me get back to you.

Sincerely,

Gerome

Hi Gerome,

Thank you. I am looking forward to your response.

Regards,

Marvin

Hi Marvin,

Thank you for your reply.

Sincerely,

Gerome

Hi Gerome,

Any update from the team?

Regards,

Marvin

Hi Marvin,

I am in talks with the appropriate team regarding this matter. Please expect a response by EoW.

Sincerely,

Gerome

Hi Gerome,

Thanks for the update. While waiting, can you please help with the follow up question below?

Is the PHY able to do JTAG boundary scan operations if the nRESET (pin 43) is held low? As currently, we have our FPGA in the same chain as the PHY responsible for driving the devices out of reset.

Also, will the device respond in the chain if the bootstrap configuration is not set to JTAG for boundary scan mode?"

Thank you kindly.

Regards,

Marvin

Hi Marvin,

I will forward these questions to the same source I am asking regarding the BDSL file.

Sincerely,

Gerome

Hi Gerome,

Thanks!

The customer has additoinal update:

"so we did some tests in the lap and measured the data coming back on the TDO line vers what was provided

If you look at the captured value

0x96a5a569

IR captured 0b0000000000000001001011010100101101001010110100100010001000000000
IR Expected 0b 10010110101001011010010101101001

You can see where the value we clock in is coming out.

The IR register of the FPGA is meant to be 8 bits wide and return 01 as the to LSBs, which all looks OK.

However, the IR of the PHY is also meant to be 8 bits wide and should capture a value of 0b11011101.

You can see that there are 9 bits of data returned and the value of all those bits is 0."

Regards,

Marvin

Hi Marvin,

I have forwarded this comment to the team.

Sincerely,

Gerome

Hi Marvin,

From team:

"Please check the following items.

1)  Please check 1 device at a time.  IR is of length 8bits , for 2 devices it should be 8+8 =16 bits. Found 17 bits , mostly in moving from one device to other device an extra cycle is added.  

2) Run at lower frequency and make sure TMS, TDI are driven on negative edge of TCK"

Sincerely,

Gerome

Hi Gerome,

Would you also answer the question below?

Marvn Arcangel said:

Is the PHY able to do JTAG boundary scan operations if the nRESET (pin 43) is held low? As currently, we have our FPGA in the same chain as the PHY responsible for driving the devices out of reset.

Also, will the device respond in the chain if the bootstrap configuration is not set to JTAG for boundary scan mode?"

Thank you kindly.

Regards,

Marvin

Hi Marvin,

Please allow me to get back to you at worst by EoD Wednesday.
Sincerely,

Gerome

Hi Gerome,

Thank you. I look forward to your response.

Regards,

Marvin

Hi Marvin,

I got a commit from our team to respond by tomorrow. Apologies for moving timeline commit.

Sincerely,

Gerome

Hi Gerome,

Have you received a response from the team?

Regard,

marvin