DP83826x in Enhanced Mode (Pin 1 floating):
1. HSDC077: Pins 28, 29, 30, 31 are pulled low with 2.49K resistors, even though Table 9-7 of SNLS647E shows that pins 28-30 are default 0. Are the pulldowns required?
2. For pin 31, is 2.49K strong enough? Should it be 1.5K if the voltage must be lower than 0.6V (Low Level Bootstrap Threshold : 3V3, p. 14 of SNLS647E) if the pullup can be as low as 7.5K (p. 15)?
3. If pin 14 is pulled up (2.49K? 4.7K will provide 2.0V, above the 1.3V threshold), please confirm that pin 19 will be a 50MHz Reference Clock output if pin 14 is pulled up (4.7K?) to select RMII MAC mode and pin 22 is left floating (default = 0 for RMII master mode). It would be very useful if setting up RMII Master Mode was explained on p. 34 of SNLS647E (include pin numbers on the PHY at least).
