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DS90UH947-Q1: PCLK detection (by using register)

Part Number: DS90UH947-Q1
Other Parts Discussed in Thread: ALP

Hi Team,

As you know, there is PCLK information in ALP Information page. I want to know if there is any register can indicate the PCLK of 947 using and 948 using.

In addition, I want to check the PCLK on 947 and 948.

For 947 PCLK, does it mean that the PCLK that 947 received?

For 948 PCLK, does it mean that the PCLK that 948 sent? 

Regards,

Roy

  • Hi Roy,

    I will look into ALP configuration for PCLK, and get back to you tomorrow.

    Regards,

    Josh

  • Hi Roy,

    The register on the PCLK is frequency counter (0x1F for 947 and 0x1B for 948) as shown in tables below.

    For 947 PCLK, does it mean that the PCLK that 947 received?

    For 948 PCLK, does it mean that the PCLK that 948 sent? 

    A PCLK of 947 is transmitted (TX), and a PCLK of 948 is received (RX). Please refer to the diagram below.

  • Hi Josh,

    Thanks for information. For 947 0x1F, I still don't know how to use the register to identify the 947 PCLK. Can you help list the step? Thank you.

    A PCLK of 947 is transmitted (TX), and a PCLK of 948 is received (RX). Please refer to the diagram below.

    So for 947, if we use external PCLK mode, the 947PCLK showing in ALP is that 947 sent out, but will it same as the external PCLK from front end? 

    Roy

  • Hi Roy,

    I still don't know how to use the register to identify the 947 PCLK. Can you help list the step?

    Are you asking that you want to control register to change the PCLK by yourself or you want to know how the register (0x1F) would be recognized as PCLK on ALP?

    So for 947, if we use external PCLK mode, the 947PCLK showing in ALP is that 947 sent out, but will it same as the external PCLK from front end? 

    Could you clarify front end? I believe the pixel clock on 947 (device information box) in ALP would be shown as external clock frequency in external mode.

    Regards,

    Josh

  • Hi Josh,

    This is my purpose. In short, I wan to know how can ALP catch the 947 PCLK. We want to implement this in our MCU side.

    want to know how the register (0x1F) would be recognized as PCLK on ALP?

    Front end means that the input LDVS video data into 947.

    Regards,

    Roy

  • Hi Roy,

    You can check the configuration on FPDLink3_Lib.py in FPDL3Base profile.

    Below is a screenshot of read TX frequency counter.

  • Hi Josh,

    Thanks for information. May you let me know where can I input the SerDes address? Or may you help invert into a .py file for us? Thank you.

    Regards,

    Roy

  • Hi Roy,

    I am not sure you are asking how to frequency counter would be configured as you asked above or how to use external PCLK mode to be implemented by MCU. If you want to use external PCLK mode, you need to set it by BIST Control (0x14).

    Regards,

    Josh

  • Hi Josh,

    I mean that we need to read PCLK value and so you suggest that we can refer to FPDLink3_Lib.py in ALP folder. But we are not sure how to modify it. For example, if we want to read deserializer's PCLK, I may need to set its address in .py file, but not sure how to modify it. 

    So we need your help to modify the .py file for us. Thank you.


    Regards,

    Roy 

  • Hi Roy,

    I referred to the FPDLink3_Lib script because you asked me how the PCLK value is read on Information tab in ALP. You can't modify FPDLink3_Lib.py since it is the object for all our ALP profiles. If you are asking that you want to add the command about reading deserializer PCLK from MCU side, your can add board.ReadI2C(DesAddr, 0x1B) for Deserializer PLCK and board.ReadI2C(SerAddr, 0x1F) for Serializer PCLK.

    Regards,

    Josh