Part Number: DS90UB960-Q1
Dear TI expert,
When I was developing the ub960, I needed to help answer the following questions：
1）When I disable the frame synchronization mode of the ub960, I cannot output images normally. What should be the register configuration in the asynchronous mode?
2）Is there a way to configure 960 for 2 lane or 3 lane camera frame synchronization (to handle hot plug or only connect 2 lane or 3 lane cameras)?
[1:0x3d] write common reg: 0x1, val: 0x2 [1:0x3d] write common reg: 0x1, val: 0x0 [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb2 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x22 [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x6e, val: 0xa9 [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb4 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x24 [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x6e, val: 0xa9 [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb6 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x26 [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x6e, val: 0xa9 [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb8 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x28 [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x6e, val: 0xa9 [1:0x3d] write common reg: 0x10, val: 0x0 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x19, val: 0x0 [1:0x3d] write common reg: 0x1a, val: 0x0 [1:0x3d] write common reg: 0x1b, val: 0xa [1:0x3d] write common reg: 0x1c, val: 0xda [1:0x3d] write common reg: 0x18, val: 0x3 [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x70, val: 0x1e [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x70, val: 0x5e [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x70, val: 0x9e [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x70, val: 0xde [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0xbc, val: 0x0 [1:0x3d] write common reg: 0x32, val: 0x1 [1:0x3d] write common reg: 0x33, val: 0x1 [1:0x3d] write common reg: 0x21, val: 0x14 [1:0x3d] write common reg: 0x20, val: 0x0
[1:0x3d] write common reg: 0x1, val: 0x2 [1:0x3d] write common reg: 0x1, val: 0x0 [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb2 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x22 [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x6e, val: 0x88 [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb4 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x24 [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x6e, val: 0x88 [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb6 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x26 [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x6e, val: 0x88 [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x5c, val: 0xb8 [1:0x3d] write common reg: 0x5d, val: 0x6c [1:0x3d] write common reg: 0x65, val: 0x28 [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x6e, val: 0x88 [1:0x3d] write common reg: 0x10, val: 0x0 [1:0x3d] write common reg: 0x58, val: 0x58 [1:0x3d] write common reg: 0x19, val: 0x0 [1:0x3d] write common reg: 0x1a, val: 0x0 [1:0x3d] write common reg: 0x1b, val: 0xa [1:0x3d] write common reg: 0x1c, val: 0xda [1:0x3d] write common reg: 0x18, val: 0x0 [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x70, val: 0x1e [1:0x3d] write common reg: 0x4c, val: 0x1 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x70, val: 0x5e [1:0x3d] write common reg: 0x4c, val: 0x12 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x70, val: 0x9e [1:0x3d] write common reg: 0x4c, val: 0x24 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x70, val: 0xde [1:0x3d] write common reg: 0x4c, val: 0x38 [1:0x3d] write common reg: 0x7c, val: 0xc1 [1:0x3d] write common reg: 0xbc, val: 0x0 [1:0x3d] write common reg: 0x32, val: 0x1 [1:0x3d] write common reg: 0x33, val: 0x1 [1:0x3d] write common reg: 0x21, val: 0x3 [1:0x3d] write common reg: 0x20, val: 0x0
Regards.
