DP83867E: DP83867E

Hi Onur,

What does it mean that 2 of the PHYs are not working? Is there no link, is data not being sent? 

Regards,

-Alvaro

Hi Alvaro, I mean we make the same connection to all of our 5 ethernet interface and we send frame and read it back. With wire shark we see the frame that we have sent but for the received frames we read it with only 3 interfaces out of 5. We did a loopback test with the PHY (between FPGA-PHY) and FPGA couldn't read the frame back in the same 2 interfaces. 

When I make a connection with other board, I see all phys 1gbps link established pin is active. I also see RGMII clock 125 MHz on both rx and tx and I also see some data is toggling. 

Is it clear now? Can you also inform a bit what to expect if we don't follow your guidelines about trace matching? 

Note: The board is not my design, I am trying to help to make it work before the re-design phase to understand the root cause.

Best regards

Onur

Hi Onur,

Please allow me another day to discuss this with my team, I apologize for not having a response ready today.

Regards,

Alvaro

Sure, I am waiting.

Hi Onur,

Play around with settings in Register 0x0086. Be sure that PHY has SHIFT mode enabled (can be checked by reading Bit 0 and 1 from Register 0x0032)

We are suggesting this because we believe the problem lies within the MAC interface, usual debug process has us checking the Skew between Clock & Data.

Regards,

Alvaro

Hi Alvaro, 

Indeed we tried to shift clock with a 0.25ns resolution and it helped. 

But my main question here is not a solution but the impact of not following the rules. 

In one interface, I have 1 data is 1 inch shorter than all other datas, control signal and clock and this interface is working. 

In other interface delta is 0.35 inch between data, and we couldn't make this interface work. 

If not matched traces only cause skews, which I expect 1 inch -> 180ps, then I don't understand why we have very hard matching requirements in your documents. ( It is 20 mil matching length requirement in data, clock and control signal in  snla387 design layout checklist.)

Hi Onur,

The guidelines in the App note are to maximize the timing margins based on best layout practices. These are the recommendations and not hard requirements.

Regards,

Alvaro

Hi Alvaro,

Thanks for the information. 

Once we measure the signals from PHY to FPGA, we see the signal rise and fall times are not very fast. (signal shape is good)

The signal stays in the defined ranges but highest voltage it can reach is 1.6V and the lowest it decreases is 250 mV.

Series resistors connected to RGMII transmit signals are set to 0 ohm. Do you think would it help to decrease the IO impedance to 35 ohm instead of the default value 50 ohm?

Best regards

Hi Alvaro,

I also see in our design that all JTAG pins are connected to a pull up resistor including TDO. 

Do you think this would create an issue?

Best regards?

Hi Onur,

Please see my replies below.

• Series resistors connected to RGMII transmit signals are set to 0 ohm. Do you think would it help to decrease the IO impedance to 35 ohm instead of the default value 50 ohm?
  • You can try to play around and see if it improves signal integrity/speed
• Pulls ups on JTAG_TDO pins
  • That's fine, no impact.

Regards,

Alvaro