SN75DP126: TMDS clock EMC issue

Hi, Jorgen

Refer to this table in the datasheet, Vsadj is only characterized between 3.7k and 5.7kohm, we can't guarantee DP126 operation at 10kohm. 

Placing the common mode choke on the TMDS output is the right approach, but they need to pick the right choke to attenuate the 148.3MHz frequency.

Thanks

David

Thanks David, the we choose 5.7kohm, or 5.6kohm.

Is there any other configuration parameter we could change to improve EMC radiated emissions on the clock frequency? I have tried different common mode choke but small or no change.

Thanks in advance.

BR

Jörgen

Jorgen

Using 5.7ohm or 5.6ohm VSADJ will reduce output signal amplitude and this will help to reduce emission. You can also do things outside the DP126 to reduce the emission by grounding or shielding your design.

Thanks

David

We managed to reduce the 148MHz clock but its harmonics are still too high, do you have any reference design with common mode choke/filter on the TMDS interface that passes the EMC test Class A? The product has a metallic enclosure which are grounded, the emission seems to come from the cable.

For example, what does HDMI_EN#, DVI 1.0 TMDS OUTPUT, do?

BR

Jörgen 

Jörgen 

The HDMI_EN# enables the DP-HDMI Adaptor ID to be accessed via DDC addresses 80h/81h when it is low (output is HDMI1.4b compliant). 

Have you tried a different cable to see if there is an improvement in the EMI result? Some cables would have better shielding than the other cables.

Can you also try to disable DP126 to obtain a EMI baseline? 

Thanks

David

Thanks. We have tried different cable and see improvement on one with integrated ferrites. However we are still outside spec on the harmonics and cannot bypass and test without SN75DP126. Do you have any Eval board for the SN75DP126 with USB-C input and DVI output that we can test with? The Clk output looks strange, not square, do you have any suggested common mode choke/matching on the TMDS_out0-4/clk, reference design we can review? I'm also interested in how the AGND and GND are supposed to be connected to meet EMC requirements?

Thanks in advance.

BR

Jörgen

Jörgen

I only have the DP126EVM design which has DP connector on the input side and HDMI connector on the output side. I can send you the board file in a private e2e message if you are interested. 

You can take a look at Murata HDMI common mode choke, here is a link to their CMC product line, https://www.murata.com/~/media/webrenewal/products/emc/emifil/cmcc/pdf/hdmi14b.ashx.

Thanks

David 

Hi David, I would appreciate the DP126EVM design, please send me the files.

BR/ Jörgen

Hi, Jörgen

Can you please accept my friendship request so I can send you the board file in a e2e private message?

Thanks

David