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DS90UB935-Q1: Optimal PLL settings for 25MHz Clock Out

Justin Bohr
Mastermind 27990 points
Part Number: DS90UB935-Q1

Hi Team,

If a 23.375MHz Ref clock is used on the deserializer side in synchronous mode, but 25MHz is needed as the clock out to the imager, would the following be the best PLL settings for Clock Out accuracy and minimal Jitter?

Ref Clk = 23.375MHz

FC = 160

FC Data Rate 4.16Gbps

HS_CLK_DIV = 4

M = 5

N = 187

Clk Out  = 25MHz

Calculated Jitter would be 1.069 ns and a Clock out error of 0%.

Is my understanding and calculations correct. Are there any better settings for lower jitter/error?

Thanks,

Justin

  • 0
    TI__Mastermind 22830 points

    Hi Justin,

    For your application, your calculations are correct for the expected jitter and and clock out error rate, but your FC data rate will be 3.74 Gbps. 

    Alternatively, you can consider using M=1 (Register 0x06 = 41) and N=37 (Register 0x07 = 25) for 0 expected jitter, while the trade-off will be a clock out frequency 25.27 MHz.