PWN_N pin low

Benjamin Williams

Part Number: DP83869HM

When we cycle power the PWDN_N pin (pin 44) is pulled low (0V). If we manually reset the device via RESET_N (pin 43), for the duration of the reset the PWDN_N pin is released and pulls up to 3.3V via the pull resistor and then when the reset is deasserted the PWDN_N pin is then asserted low again, which goes against the datasheet that says this pin is by default an input.

This behaviour does not make sense as the device is supposed to have PWDN_N (pin 44) configured as an input by default to allow for external control of power-down mode. We have a resistor-cap filter on the RESET_N pin with a duration greater than 200ms before the voltage on this pin is greater than 2V (the Vih minimum limit) so the device should be powering up sufficiently.

We are also operating with 2 voltage supply rails (so have thus left the 1P8 pins floating as the datasheet requires).

over 3 years ago

0 Gokul Koraganji over 3 years ago

TI__Mastermind 19250 points

Hi Benjamin.

Can you please share the plots/waveforms of the described behavior? Is this PWDN_N pin connected to a controller/host?

--
Regards,
Gokul.

0 Benjamin Williams over 3 years ago in reply to Gokul Koraganji

Prodigy 30 points

The waveform is exactly as I have described it. Whenever the RESET_N pin is asserted the PWDN_N pin is released. We are using a push button to allow us to manually assert RESET_N and PWDN_N is connected to a host FPGA with a high-z on this pin as the device is blank.

The behaviour goes against the datasheet as this PWDN_N pin is supposed to, by default, be an output in the high-z state. We have a pull upon this pin so it should pull up, which it does not.

0 Gokul Koraganji over 3 years ago in reply to Benjamin Williams

TI__Mastermind 19250 points

Hi Benjamin,

Sorry for the delay in response. I will try to reproduce this locally tomorrow and get back to you.

Is host FPGA programming 0x1E register immediately after reset by any chance?

--
Regards,
Gokul.

0 Benjamin Williams over 3 years ago in reply to Gokul Koraganji

Prodigy 30 points

The host FPGA is blank and does not program anything. The PWDN_N pulls low. If I try to drive this pin high from the FPGA then the pin reads 0.7V. there is contention on the pin. After removing the PHY from the board the pin is able to pull high. So this is my reason for suspecting the PHY is trying to pull this pin low. It does not make sense to me as the PHY should, by default, have this pin as an input?

0 Benjamin Williams over 3 years ago in reply to Benjamin Williams

Prodigy 30 points

However, as previously mentioned, if I pull the RESET_N pin low, the PWDN_N pin is able to pull high.

0 Gokul Koraganji over 3 years ago in reply to Benjamin Williams

TI__Mastermind 19250 points

Hi Benjamin,

I was not able to recreate this in my setup. I did the same you did, but I see PWDN pin always pulled high.

To look at potential root-causes, can you please capture the waveforms?

RESET_N rising edge to PWDN_N going high
RESET_N falling edge to PWDN_N going low

I am interested to see the delay between the transitions of RESET_N and PWDN_N. That might give us some clue on what's going on.

Can you please share the board schematic too?

--
Regards,
Gokul.

0 Gokul Koraganji over 3 years ago in reply to Gokul Koraganji

TI__Mastermind 19250 points

Hi Benjamin,

Do you have any updates on this?

--
Regards,
Gokul.

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PWN_N pin low