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DS250DF810: Customer Schematic Review

Michael Balourdas
Expert 5455 points
Part Number: DS250DF810
Other Parts Discussed in Thread: DS250DF410

Hello,

My customer has a new schematic using DS250DF810 that I could use some help reviewing. I'd prefer not to post the schematic here, but using this for tracking purposes.

Thanks,

Michael

  • 0
    TI__Mastermind 36623 points

    Hi Michael,

    Thanks for posting this on E2E, it is helpful for tracking.

    Here are my notes from reviewing the schematic:

    • Power Supply Decoupling (Good)
    • High Speed Traces (Good)
    • Cal clk daisy chain (Good)
    • ADDR0/1 (Good): Configures addresses 0x30 & 0x36
    • EN_SMB (Good): Configures SMBus slave/target mode
    • SDA/SDC (Good): Please ensure appropriate pullup resistors are connected to these nets.
    • READ_EN_N: Please ensure that this is pulled high or left floating while in SMBus target mode.
    • INT_N (Good)
    • TEST[7:0] (Good)

    Regarding questions you had shared:

    1. Can they use a 25MHz clock source from an external clock generator instead of the Oscillator X3? Then connect CAL_CLK_OUT from U46 to U75 CAL_CLK_IN pin.
      1. Please see the description for CAL_CLK_IN below.  As long as the external clock generator meets these requirements, I would not anticipate any issues.
      3. It is common to cascade CAL_CLK_OUT to CAL_CLK_IN in a system with multiple retimers.  I would not anticipate any issues because of this.
    2. Is the I2C address setting correct?
      1. The I2C address setting appears correct, but you should confirm which addresses they are trying to set the devices to.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    TI__Expert 5455 points

    Thanks so much Drew! A few return questions from the customer based on the feedback:

    1. They use SMBus from CPU to control the mux to switch to the desired channel as show in the attached block diagram (sent via email). Can you sanity check this vs the schematic?
    2. Is there any way to implement polarity swapping on either the transmitter side or receiver side to simplify the layout?  
    3. The mux is set in SMBus slave mode. So READ_EN_N pin should be pulled high or left floating for normal operation. ALL_DONE_N pin can be left floating. These two pins are not needed to connect to GPIO of CPU to report the status. All the communication can be done through SMBus. Is that correct?
    4. The I2C address notes are changed to 0x30 and 0x36 respectively to reflect HW setting.  
    5. Since this SMBus bus is 3.3V tolerant, those two mux are connected to 3.3V SMBus master.   
  • 0 in reply to Michael Balourdas
    TI__Mastermind 36623 points

    Hi Michael,

    1) To be clear, in the block diagram, the retimer is playing the role of MUX-1 and MUX-2, right?  Something that should be noted is that the retimer package is laid out for unidirectional operation (all tx / rx are on one side of the package).  The current mux arrangement they have could make routing challenging.  Not sure if this would further complicate routing, but perhaps they could use one retimer for all ingress and another retimer for all egress as opposed to one retimer per port.  Alternatively, 2x DS250DF410/QSFP port could be considered.

    I also noticed the block diagram has QSFP56-DD ports.  Please note that this is a 25G retimer and does not support 56 Gbps PAM4.

    2) It is possible to invert the polarity of the output driver.

    3) Yes this is correct.

    4) Good.

    5) No concerns here.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    TI__Expert 5455 points

    Hi Drew,

    Thanks for the feedback.

    1) Yes the MUX-1 and MUX-2 are referring to the retimer. After a layout study, using 2x DS250DF410 instead did not help. The end customer defined the lane mapping, so my customer can’t change it.

    2) They have swapped the polarity on some of the TX ports. Can you double check the new schematic?

     

    Additional question on the power on reset: What is the requirement of the 2.5V power up timing and 25MHz clock available time? Can the clock be ready later than 2.5V?

    Thanks,

    Michael

  • 0 in reply to Michael Balourdas
    TI__Mastermind 36623 points

    Hi MIchael,

    The P/N swaps that are highlighted in the schematic look fine.

    Regarding the 25 MHz clock, we would not expect any issues with supplying the clock after 2.5V.

    Thanks,

    Drew