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PCA9306 Vref1 current when EN low

Mike Roberts
Prodigy 10 points

I am interfacing a 3v3 SMBus to 5v system where the 5v system (master) will power down during sleep but the 3v3 side (slave) will remain live.

Hence the concern as to the drain on the Vref1 (and SDA1, SCL1) when the Vref2, EN, SDA2, SCL2 are all low/powered down.

Clarification on this would be appreciated.

Many thanks

Mike

  • 0
    TI__Intellectual 1930 points

    Hello Mike,

    This should not be an issue since VREF2 and EN are powered off of the 5.5V supply.  When the 5.5V supply is at 0V, the SDA0, SCL0 and VREF1 pins will be disabled (High-Z).   The only issue would arise if the 5.5V supply does not go all the way to 0V.   If it is above ~0.7V, there will be leakage on the SDA0, SCL0, and VREF1 pins.

    Regards,

    Akhil.