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DS160PR822: Link up issues oscillates between L0 <--> Recovery

Sricharan Challa
Prodigy 10 points
Part Number: DS160PR822

Hi,

I am using DS160PR822NJXR in a new design. I see that link is not at all stable and keeps moving from L0 to recovery to L0. I tried all the strap settings but no luck. Here is my setup

 

Xilinx V7 FPGA (GTH) <--> 1m cable <--> DS160PR822 <--> PCIe Gen3 capable endpoint. 

 

can you please help here. 

 

regards,

Sricharan

  • 0
    TI__Guru* 93670 points

    Hi Sricharan,

    At Gen3, i would have expected solid L0 session.

    1). Any way to force Gen1 or Gen2 just to make sure there is no link recovery?

    2). Please make sure 1m cable insertion loss is within the limit(<22dB)? 

    2). Is it possible to use a shorter cable length just to check if this is related to the cable insertion loss?

    3). I am not sure if you've done signal integrity study to make sure with your cable, connectors, and pcb material we can meet these insertion loss requirements.

    Please let me know.

    Regards,Nasser