DS90UH947-Q1: ESD failed

Hey Roy,

Thanks for the information. 

Roy Chou1 said:

As title, we failed the ESD test when test item was air 4kV and we used 947 internal pattern generation to bring up the panel. The failed behavior was that black screen when did the ESD test, but auto recovery. 

It's not very clear what is being described here? 
What do you mean by auto recovery?
Did the device get ESD damaged and how can it recover?
Please see Abs max, ESD rating and recommended operations below. Can you let me know what ESD limits are you referring to?

Are you able to get lock between the 947/948 ? 
Are you getting valid PCLK on Des side?
Can you provide a register dump of the Ser/Des at the failing state?

Roy Chou1 said:

And we didn't see the issue when using 948 internal pattern generation. So we think the root cause may be link of SerDes. 

What do you mean by didn't see the issue? Does that mean you have valid video output on the display when using internal patgen of 948?

In order to provide a more accurate isolation, would you be able to complete the attached excel sheet testing using TI's Analog LaunchPad (ALP) TI software ?

Testing - Video pattern - timing Ser-Des.xlsx

Regards,
Fadi A.

Hi Fadi,

Thanks for comments. This is system-level ESD test. And it's hard to describe the test result in English. 

In short, the screen is flicker when did the ESD test, but normal when after ESD test. 

We can't measure the lock pin status or connect ALP when doing the ESD test because it will damage the instrument.

So we want to know if we have registers can indicate the root cause like 98x series have lock sts changed. 

Regards,

Roy

Hey Roy,

Roy Chou1 said:

In short, the screen is flicker when did the ESD test, but normal when after ESD test. 

Ok so only during the ESD testing the screen flickers, but once the ESD testing is done, the screen goes back to normal correct? 

Roy Chou1 said:

We can't measure the lock pin status or connect ALP when doing the ESD test because it will damage the instrument.

It's important to be able to capture the lock signal during the screen flicker because the LOCK output reporting pin serves the purpose of validating the link integrity of the connection between the SER and DES. When the LOCK status is high, the PLL in the DES is locked and validates that the data and clock have been recovered from the serial input and is available on the parallel bus and PCLK outputs.

If the LOCK status is low, then the PLL is not locked, meaning that the serial data isn’t being fully recovered and the data at the output does not represent the data transferred from the SER. For example, if you are using a TI  EVM, this status can be easily checked by monitoring the LED labeled “LOCK” on the DES EVM.

Roy Chou1 said:

So we want to know if we have registers can indicate the root cause like 98x series have lock sts changed. 

On the 948 side, you can check register 0x1C bit 0 for lock status.

Regards,
Fadi A.

Hi Fadi,

Thank you for your comments. 

For 948 0x1C[0], does the bit indicate the lock status at that time? Or if the lock status changed the bit should be '0'. I concern that the unlocked status only occurred when we was doing ESD test. After ESD test, it will be recovered. So we may need lock status changed register. 

In addition, as you can see below, our chip can meet below system level ESD, does it mean that we can suffer this spec and IC won't be damaged or abnormal in this spec? Thank you. 

Regards,

Roy

Hi Fadi,

Thanks for information. Actually, the ESD level is only 4kV contact with IEC 61000-4-2. The ESD gun hit case screw(GND). We found the panel show black screen or abnormal picture output when we was doing ESD test, but auto-recovered after ESD test.

Actually in 4kV contact, we need to pass class A level which means that we can't see any abnormal output patter doing ESD. 

I want to know whether 947 or 948 has specific registers that can indicate the SerDes signal affected by ESD test or not. For example, in 983/984, we have user FIFO status or lock status changed can check.

In other words, if there is register can indicate the LVDS signal(948output) or FPDlink signal(947output) were normal when doing ESD. That's also ok.

Regards,

Roy 

Hi Roy,

You can check register 0x1C on the 948 side to monitor lock status. 

Regards,
Fadi A.

Hi Fadi,

If the scenario is that the Serdes lock was lost when we was doing ESD. But after ESD, the lock status recovered. What will the 0x1C report after ESD test?

Regards,

Roy 

Hey Roy,

When doing ESD testing, loss of lock is expected. The passing criteria is if our device recovers after losing lock. If it recovers then it's passing if it doesn't recover then it's a fail. 0x1C will report the current state of the lock at the time of reading this register.

If lock is established, bit 0 will be high, if no lock is established it will be low. 

Regards,
Fadi A.

Hi Fadi,

Thanks for your comments. May you let me know the response time of the 0x1C register. We plan to use MCU to read the register status during ESD test. As you know, ESD energy is inserted at the moment. I'm wondering if we can get the true data when doing ESD.

Regards,

Roy 

Hey Roy,

I'm not sure you'll have I2C communication during ESD discharge peak. I think it's best to monitor lock status on the scope if you'd like to see the high/low toggle. For capturing accurate register information you need to be in a stable power state.  

Roy Chou1 said:

In other words, if there is register can indicate the LVDS signal(948output) or FPDlink signal(947output) were normal when doing ESD. That's also ok.

On 947 side you have 0x0C register which shows valid PCLK is detected on the ODLI input and cable link is detected as well.

Regards,
Fadi A.

Hi Fadi,

Thanks for information. Actually, it's dangerous that measure the signal like lock or I2C during the ESD test. So that's why I want to check if there is any register can record the fault when there was fault event like lock lost.

I want to check 0x0C register information. From our scenario, our panel only showed the abnormal output when doing ESD test. But after ESD test, it can be recovered automatically. So we want to know whether the abnormal phenomenon is from FPD-link or not. Unfortunately, we didn't face the issue when using TCON patgen or 984patgen. So customer think the reason is from FPD-Link.

So I want to find some registers that can indicate that there is no fault when doing ESD test to point out our SerDes link is ok when we was doing ESD test. 

For 0x0C[3] and 0x0C[1], can I say if there is no error detected after doing ESD test which means the link between SerDes was normal during ESD test?

For 0x0C[2], I think the bit is that when we use oLDI input, is it correct? For the case, we used 947patgen.

For 0x0C[0], I think the bit can't indicate the useful information. Because we found the panel output is normal when after doing ESD unless we can monitor the bit during ESD test. Because ESD test was inserting energy at a moment, I'm not sure if we can read the correct data when during the ESD test. 

Regards,

Roy

Hi Roy,

I'm currently out of office. I will review and get back to you no later than Wednesday 11/16.

Regards,
Fadi A.

Hey Roy,

You can run MAP tool testing to see customer link margin, etc. but as far as what you are trying to do, it's not feasible, there is no stick bit for checking lock loss on 94x devices, but if black screen is only present momentarily, it is likely a result of lock loss. 

Regards,
Fadi A.

Hi Fadi,

Do you mean that we can use MAP tool to check the link quality margin? More margin means that it can accept more ESD energy? 

Do you have criteria for the spec?

Regards,

Roy

Hi Fadi,

One information want to align with you. Attached image is measured by source IC vendor. It said that our 948 didn't send DE signal when did the ESD test. The duration is about 1.x ms. But we didn't meet the issue using 948patgen, but 948patgen used lower PCLK due to limited PCLK.

If there is any register can check the DE status?

Regards,

Roy

Hey Roy,

So HS and VS are checked also and they look fine but only DE is missing?

Roy Chou1 said:

Do you mean that we can use MAP tool to check the link quality margin? More margin means that it can accept more ESD energy? 

Do you have criteria for the spec?

Correct. see link for info on how to install and test criteria. 

https://www.ti.com/lit/ug/snlu243/snlu243.pdf?ts=1668609864120&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards,
Fadi A.

Hi Fadi,

We will use MAP to check the SI performance.

Fadi Abdulhameed said:

So HS and VS are checked also and they look fine but only DE is missing?

Because we used DE mode so we don't check the HS/VS data.

Regards,

Roy

Hey Roy,

Roy Chou1 said:

948 didn't send DE signal

Can you also check the lock signal while DE signal is lost ? Is this DE signal loss happening in conjunction with loss of lock? 

Regards,
Fadi A.