DP83848I: Hardware schematic design problems

Hi Rhea,

The MDIO pin requires a 1.5 kΩ pullup resistor, and the center tap of the transformer needs to connect to supply. The later will definitely cause packet loss issues if not followed correctly. Please see section 7.2.1.1 of the datasheet for the correct TPI network circuit. 

Thanks,

David

Hi David,

1. After the new modification, there is no improvement, and the packet loss is still very serious.

2.Another question is that the design is not according to the official reference, but we can communicate with each other. Please help to solve the reason.

① The hardware design diagram of (PHY)DP83848KSQ and network transformer is as follows: TX and RX differential pair of PHY are connected with transformer, TXRX differential pair is grounded through 49.9R resistance and capacitance; The transformer center tap is connected to 3.3V.

② TX/RX differential pair of (PHY)DP83848VVVBI is connected to 3.3V through 49.9R resistance; The transformer center tap is grounded through a 0.1UF capacitor.

In the above content, the hardware design of the network transformer in ① is different from the circuit recommended on the official website, but there is no problem in use. Why can it be used normally when it is different from the official design?

②The hardware design of the network transformer in the PING network port is different from the official recommended circuit. Packet loss and delay occur in the ping network port. But it also communicates. Why, unlike the official design, does it communicate?

Many thanks~

Hi Rhea,

The images you pasted are extremely pixelated. Please send me a searchable PDF copy of the schematic.

Thanks,

David

Hi David,

Smart DDC.pdf

Hi Rhea,

I am a little confused with the two designs. Which one is having the problem? I will review that ones schematic. Please send me a datasheet for the JNET1 connector and RJ1 connector. These do not look like typical RJ45 connectors.  

The MDI section should look EXACTLY like the below image from the datasheet. If it does not, this would explain the packet loss issue.

Thanks,

David

Hi David,

This one is having the problem.

JNET1 corresponds to HR911103A; RJ1 corresponds to HR961160A.

  HR911103A.PDFHR961160A.pdf

Thanks!    

Hi Rhea,

I see the center taps (P3 and P6) are not connected to 3.3V. The proper schematic should look like this: 

Thanks,

David

Dear David,

Thanks a lot for your reply and support!

The customer has already changed their design and the problems were still happened.

PCB1356802(4164_CE-MAIN)(OPS工艺）.PcbDoc

I have uploaded the Layout of the customer's design, which can be opened by Altium Designer.

Could you please help me to have a look on this layout?

Really appreciate!

Best regards,

Xenon Li

Hi Xenon,

Please go through the PHYTER layout guide as well as the Ethernet PHY Layout Checklist and let me know if you have specific questions.

Thanks,

David