• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 34 subscribers
  • Views 326 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH0341: RXCLK output frequency for 270 Mbps mode of SDI video

Miheer Bariya
Prodigy 10 points

Part Number: LMH0341

Hi, 

We are not able to understand timing for RXCLK output from this IC for 270 Mbps mode of SDI. As per data sheet timing diagram Figure 3, it is 331 MHz. However. How this can be true for 270 Mbps mode with 5-bit parallel data? We are taking this IC data to FPGA host and in order to architect our FPGA design, we really need to understand the RX clock frequency of this IC. Please respond with details.

Thanks,

Miheer

  • 0
    TI__Guru* 93570 points

    Hi Miheer,

    What you are referring to is the fastest clock rate - note this part runs at 3Gbps. In general RX clock is one tenth of the data rate and it is DDR. So for 270Mbps, RX clock is actually at 27MHz. At this rate, we have 5 LVDS pair data and with DDR we would get 5X2(DDR)X27=270Mbps. For 2.97Gnps or 3G, we would  have 5X2X297 or 2.97Gbps.

    Regards,Nasser