DP83867IS: Clock anomaly monitoring function

Hiroaki Yuyama TED

Part Number: DP83867IS

Dear, support Team.

Our user is using Ethernet PHY DP83867IS with 25MHz oscillator on SGMII.
A 25MHz oscillator's duty cycle can exceed 40% to 60%.
Effectively, the link up will come off at 34.56% or less.
If the DP83867IS is out of link up, is there a way to check in the registers if the PLL lock out?

Best Regards,
Hiroaki Yuyama

over 2 years ago

0 David Creger over 2 years ago

TI__Mastermind 26642 points

Hi Hiroaki,

Duty cycle of 40% to 60% is recommended. Please ensure the oscillator meets this requirement, and let me know if it fixes the issue.

Thanks,

David

0 Hiroaki Yuyama TED over 2 years ago in reply to David Creger

Expert 1720 points

Hi, David-san,
Thank you for your reply.

Yes, the oscillator input duty cycle from 40% to 60% will link up normally.
However, when the duty cycle reaches 34.56%, the link up is lost.
We would like to know if there is a signal from the DP83867IS registers when the linkup is lost.

Best Regards,
Hiroaki Yuyama

0 David Creger over 2 years ago in reply to Hiroaki Yuyama TED

TI__Mastermind 26642 points

Hi Hiroaki-san,

Bit[2] of register 0x1 will show the link status.

Thanks,

David

+1 Hiroaki Yuyama TED over 2 years ago in reply to David Creger

Expert 1720 points

Hi, David-san,
Thank you for your support.

Now I understand how to read from a register when linkup is lost.

Best Regards,
Hiroaki Yuyama

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DP83867IS: Clock anomaly monitoring function