DP83825I: Design review

Hi JH,

I will review the schematic and get back to you in 5 business days.

Thanks,

David

Hi David,

Are there any updates?

Thanks,

JH

Hi JH,

Here are my comments:

1. There are insufficient caps on the VDDIO and VDDA3V3 pins. Please see below.

2. C679 and C681 should be 1uF, not 100pF.

3. C352 should be 10nF.

4. Consider isolating the connector ground from digital ground, as shown in Figure 19 of the datasheet.

Thanks,

David

Hi David,

Please advise on the following inquiry.

2. Below is the reset min timing in the DS. Is that time mandatory?

Thank you.

JH

Hi JH,

The minimum reset pulse width spec of 25us is mandatory, yes.

Thanks,

David

Hi David,

There is a difference between the above and the following thread.

Please advise which one is correct.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/886720/dp83825i-dp83825i-reset-timing?tisearch=e2e-sitesearch&keymatch=DP83825I%252525252520reset#

Thanks,

JH

Hi JH,

I did not see this discrepancy. Please follow Vikram's guidance in the other E2E post. 1us should be sufficient.

Thanks,

David