Part Number: DP83822I
Hi,
For the 100BASE-TX Duty Cycle Distortion Test (DCD) there is a "01010101 NRZ" pattern needed.
How can I generate this pattern with the DP83822I PHY?
Thanks and best regards,
Patrick
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Part Number: DP83822I
Hi,
For the 100BASE-TX Duty Cycle Distortion Test (DCD) there is a "01010101 NRZ" pattern needed.
How can I generate this pattern with the DP83822I PHY?
Thanks and best regards,
Patrick
Hi Patrick,
Please see register 0x0027 in the datasheet.
Thanks,
David
Hi David,
Can you please be a bit more specific about how to set register 0x0027 for a 100BASE-TX "01010101 NRZ" pattern.
Regards,
Patrick
Hi Patrick,
Please see this snippet from a Tektronix app note:

To run the Duty Cycle Distortion test, you should not need to explicitly generate a 0-1-0-1 pattern. Rather, the oscilloscope will find the 0-1-0-1 pattern within the test pattern which SNLA266 shows how to generate.
I should not have mentioned it, but register 0x27 can be used to explicitly generate a 0-1-0-1 pattern as described in detail here, but you should not need to do this:

Thanks,
David
Hi David,
When I set register 0x0027 to 0x0001 and register 0x0428 to 0x0010 (single 0 after a 1) I get the following signal at the transmitter:
But I expect to get this:

Regards,
Patrick
Hi Patrick,
What is the reason for wanting to do this? There is no need to set this to run the compliance test.
Before writing to register 0x0027 and 0x0428, have you forced the speed to 100Mbps in the Basic Mode Control Register? You can do this by writing 0x2100 to register 0x0000.
Thanks,
David
David,
Yes, speed has been set to 100Mbps in Basic Control Register.
Regards,
Patrick
Hi Patrick,
Please try running the compliance test following the direction of SNLA266 without writing to register 0x0027 or 0x0428. Let me know the results.
In parallel, please send me a screenshot of reading register 0x0000, 0x0027 and 0x0428 after writing to them to ensure the write was performed correctly.
Thanks,
David
Hi David,
The write to the register was correct. It turned out that after a correct register write it is neccessary to have an edge on the MDC signal to get the right pattern.
The following screenshot shows this behaviour:
Channel 2 shows the edge on MDC. After around 250ns the expected pattern shows up.
Regards,
Patrick
Hi Patrick,
The normal implementation is to use a continuous MDC clock. You can add an additional read at the end of your write sequence to fix this issue, then. Glad to hear the expected pattern is showing now. Is there anything further I can help with?
Thanks,
David
Hi David,
It would help to have this mentioned in the datasheet of the DP83822I. Especially if one reads the following in the datasheet:
If this is not known one could try for ever to generate a needed pattern.
For the time beeing no further help is needed.
Thanks and best regards,
Patrick