P82B96: Interface forum

Hello,

I will respond by noon 10/24/2022.

Regards,

Tyler

Hi Tyler

Thank you for your reply

The task I was given by a customer is to provide an indication of the allowable capacitance for cables when using relatively short cables (less than 10m).
I found understanding the "10.2.1.2 Detailed Design Procedure" very helpful for this task. And I calculated the 25m cable example myself to try to get a better understanding.
However, even if I apply the values ​​in Table 1 to the equations in figures 7 to 9, I could not get 490ns for SCL delay and 570ns for SDA delay.
So, I also suspected that calculating the delay might require special calculations related to the device architecture, so I posted the question.

From your answer, it seems to be very difficult for you to find the meaning of the constants and coefficients that I asked last time.

Could you please answer the following three questions instead?
1. Calculation process of "the falling edge of SCL is delayed 490 ns".
　I have a feeling that the sum of the following values ​​will roughly match 490ns.
　　· Falling delay value calculated from the output impedance of the TX/TY terminal estimated from the VOL characteristics and the cable capacitance.
　　· Propagation delay of each part
　I want to check if it is correct, so please show me a model of the calculation process.
2. Calculation process of " the SDA rising edge is delayed 570 ns."
3. Why define "the clock is stretched 400 ns".
　From the context of "10.2.1.2", I think that since the required Low period is 635ns short of the standard 1300ns, it should be simply written to program Low period=1935ns. (clock stretch=635ns)

Best regards,
Masaki

Hi Masaki,

To help answer these questions, please review this e2e post:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/870398/p82b96-how-to-calculate-the-bus-delay?tisearch=e2e-sitesearch&keymatch=P82B96%252525252520calculation#

I think this helps to explain roughly where these delays come from. 

Regards,

Tyler

Hi Tyler,

Thanks for pointing me to a post that might be helpful.

Unfortunately, Bobby's post doesn't seem to fully answer my question.
Regarding 400ns, Bobby's answered that it depends on the architecture of the device, but there seems to be no confirmation.
Also, regarding the 490ns calculation, he says that the 45ns calculation does not fit.
I suspect that Bobby made a mistake in applying the delay values ​​from the "7.9 Switching Characteristics" table.
Since the load conditions in TEST CONDITION in the table in section 7.9 and the load conditions in figure 10 and Table 1 are different, I thought that there was a difference in the transient response time.
Therefore, subtracting the values ​​in notes (1) to (4) in the table in section 7.9 from the delay values ​​in the table, and calculating the transient response time again, I got a total of about 485ns.
However, when the calculation of 570ns is done with the same idea, the total exceeds 800ns!
Something is wrong with my idea too.
From the above, I think that the delay values ​​in the table in Section 7.9 include the transient response time due to the load, but since it is difficult to separate it, I will simply consider the worst value of the device propagation delay.
And I will add the transient response time due to the load.
I think that the delay margin will be too large, but I think we can avoid the situation where the system does not work.
Do you have any suggestions for this?

The datasheet for the P82B96 is very difficult to understand because the calculation assumptions are sorely omitted.

Please tell me one more thing. The P82B96 is also sold by NXP and the datasheet is very similar, but where was it originally developed?

Best regards,
Masaki