DP83TD510E: rmii_ovf_sts = 1 (RMII fifo overflow indication) when sending TX packets on RGMII

Can you confirm that we should ignore the rmii_ovf_sts when using RGMII?

Steffen,

To confirm that, we will need to experiment to see why the status flag is being driven; I will need you to check the ppm differences between:

• Reference clocks
• PHY & link partner
• PHY reference clocks

Sincerely,

Jason Lee

Hi

The reference clock for the MAC (Zynq Ultrascale+ MPSoC FPGA) is a 33.33 MHz, 20 ppm oscillator. In the FPGA, the 33MHz clock goes through an RPLL and a MMCM. The resulting 125MHz clock is used to drive the TX_CLK, TX_CTL and TX_D(3:0) from the MAC to the PHY  (10 Mbit mode, so TX_CLK is 2.5 MHz.)

The reference clock for the PHY (XI input) a 25 MHz, 20ppm oscillator.

The link partner is a TI eval board: DP83TD510E-EVM. It has a 25MHz (50 ppm) oscillator, according to the schematics pdf file in “design files” in https://www.ti.com/tool/DP83TD510E-EVM

 We also tried a setup where the link partner is another PHY on our board, with its own 25MHz 20ppm oscillator, and the overflow indication still occurrs in the PHY.

Steffen,

I will consult with colleagues who have DP83TD510 expertise and get back to you shortly; Please keep me updated with any changes!

Sincerely,

Jason Lee